diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-07 19:03:24 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-10 10:26:43 +0100 |
| commit | a681e6d63285b879bb9bab0bd79e2021e6dcbda1 (patch) | |
| tree | 14886e1a124ff05f6537df341bdf3497d7c00e3f /arch/arm64/boot/dts/renesas/r8a7796.dtsi | |
| parent | 9fccf4d6103eeb5db88c1ae026d61b87f722414a (diff) | |
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 454e1292f910..b951f5ffe9e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -61,6 +61,13 @@ cache-unified; cache-level = <2>; }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; }; extal_clk: extal { |