diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2018-09-26 12:53:57 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-09-26 13:37:52 +0200 |
| commit | cd7ab133db383204c9712e1c6fe9dcaa14f90955 (patch) | |
| tree | 7333acaacd2e623a2ac0c6e29169ec5088c8440d /arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | |
| parent | e4f3fb4909677c33f97a871af56b9115f3e178b4 (diff) | |
arm64: dts: rockchip: Enable SPI NOR flash on Rock64
The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.
This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3328-rock64.dts')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 9ee4f57557f3..2170cf63845e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -290,6 +290,18 @@ }; }; +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; |