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authorHuibin Hong <huibin.hong@rock-chips.com>2018-07-06 16:03:57 +0800
committerHeiko Stuebner <heiko@sntech.de>2018-07-07 13:02:27 +0200
commitd0414fdd58eb51ffd6528280fd66705123663964 (patch)
tree97686378872091e797f103d255cb044a4983bfd5 /arch/arm64/boot/dts/rockchip/rk3328.dtsi
parent8559bbeeb849283003138648ada9098a7eb63632 (diff)
arm64: dts: rockchip: corrected uart1 clock-names for rk3328
Corrected the uart clock-names or the uart driver might fail. Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") Cc: stable@vger.kernel.org Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3328.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 2f38ff2f1465..3f5a2944300f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -297,7 +297,7 @@
reg = <0x0 0xff120000 0x0 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "sclk_uart", "pclk_uart";
+ clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 4>, <&dmac 5>;
dma-names = "tx", "rx";
pinctrl-names = "default";