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authorShunqian Zheng <zhengsq@rock-chips.com>2018-01-09 09:42:21 +0800
committerHeiko Stuebner <heiko@sntech.de>2018-02-12 09:40:11 +0100
commitba2b043e90f264df1969c4428bc89d7121e475e8 (patch)
treea64e2d81be7ea79340dc6745dbcca97067a20400 /arch/arm64/boot/dts/rockchip/rk3399.dtsi
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff)
arm64: dts: rockchip: Add cif test clocks for rk3399
There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 7aa2144e0d47..85b30c984acf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2293,6 +2293,23 @@
};
};
+ testclk {
+ test_clkout0: test-clkout0 {
+ rockchip,pins =
+ <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ test_clkout1: test-clkout1 {
+ rockchip,pins =
+ <2 25 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ test_clkout2: test-clkout2 {
+ rockchip,pins =
+ <0 8 RK_FUNC_3 &pcfg_pull_none>;
+ };
+ };
+
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;