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authorWilliam Wu <wulf@rock-chips.com>2016-11-07 20:08:49 +0800
committerHeiko Stuebner <heiko@sntech.de>2016-11-15 16:22:24 +0100
commitfe7f2de1c6ca27548559f75e34682506dea6bd07 (patch)
treebb8f0a4ba12f5f7e8664b317b3b9f6f8e0ab657c /arch/arm64/boot/dts/rockchip/rk3399.dtsi
parent1bc60beec02d3b3ce87209bda69c2d94630beb6e (diff)
arm64: dts: rockchip: add usb2-phy otg-port support for rk3399
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu <wulf@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index fc30b57ac557..0ee4220ddf08 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1128,6 +1128,16 @@
interrupt-names = "linestate";
status = "disabled";
};
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
};
u2phy1: usb2-phy@e460 {
@@ -1145,6 +1155,16 @@
interrupt-names = "linestate";
status = "disabled";
};
+
+ u2phy1_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
};
emmc_phy: phy@f780 {