diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-03-31 13:20:45 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-05-14 11:43:46 +0900 |
| commit | ba6f7011bde0ba762f89e7c544d1e0f24dc1bd4e (patch) | |
| tree | 83a025ef5ca234928efdbeeeb52e461072aab943 /arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff) | |
arm64: dts: uniphier: add input-delay properties to Cadence eMMC node
Since commit a89c472d8b55 ("mmc: sdhci-cadence: Update PHY delay
configuration"), PHY parameters must be specified by DT.
The hard-coded settings have been converted as follows:
- SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy
- SDHCI_CDNS_PHY_DLY_EMMC_SDR -> cdns,phy-input-delay-mmc-highspeed
- SDHCI_CDNS_PHY_DLY_EMMC_DDR -> cdns,phy-input-delay-mmc-ddr
The following have not been moved:
- SDHCI_CDNS_PHY_DLY_SD_HS
this is unneeded in the eMMC configuration
- SDHCI_CDNS_PHY_DLY_EMMC_LEGACY
this is never enabled by the driver as it is covered by
SDHCI_CDNS_PHY_DLY_SD_DEFAULT
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 6193f11acb78..e4499ff37d51 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -384,6 +384,9 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; }; soc-glue@5f800000 { |