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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-04-04 11:04:37 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-05-14 11:43:46 +0900
commite345eded5bda437417507f3591d53c39c326b90a (patch)
treebc64067c0c5a07d8398e760a8b477d528a626b8c /arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
parentba6f7011bde0ba762f89e7c544d1e0f24dc1bd4e (diff)
arm64: dts: uniphier: add cdns, phy-dll-delay-sdclk(-hsmmc) for eMMC
Adjust the PHY parameters for more stable access to the eMMC device. Set the SDCLK output delay value to 21 (including HS200/400 modes). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi')
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index e4499ff37d51..c85e6e246533 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -387,6 +387,8 @@
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
+ cdns,phy-dll-delay-sdclk = <21>;
+ cdns,phy-dll-delay-sdclk-hsmmc = <21>;
};
soc-glue@5f800000 {