summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-10-24 00:21:37 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-10-24 02:12:38 +0900
commitb6e5ec203be3cfc0a3aeb128520ab72438495470 (patch)
tree44a48436226f3b13cde466e7c70840b0db170871 /arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
parent15e85695e5009f6ba7aef05306d69f1ffc021df2 (diff)
arm64: dts: uniphier: add eMMC hardware reset provider node
Add mmc-pwrseq-emmc node to perform standard eMMC hardware reset procedure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi')
-rw-r--r--arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index fe3a193f2410..f55b14b8e92c 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -7,6 +7,8 @@
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
+#include <dt-bindings/gpio/gpio.h>
+
/memreserve/ 0x80000000 0x02000000;
/ {
@@ -124,6 +126,11 @@
};
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
@@ -317,6 +324,7 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
+ mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;