diff options
| author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-01-30 12:22:12 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2023-07-25 11:57:52 +0200 |
| commit | c643c18cbef9376e4297b557fa631b3637f53399 (patch) | |
| tree | 162e8ec0cd0b0ae4d90ee58c28689aa2cbb85a7d /arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | |
| parent | ac715584705a518fd06df5903a686c790aad9037 (diff) | |
arm64: dts: ti: k3-am625-verdin: add r5/m4 reserved memory and mboxes
Add r5/m4 reserved memory and mboxes as done in TI AM62 SK board.
Upstream-Status: Pending
State in mainline is not clear, this would need to be investigated
before sending patches.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index b394d396ddcd..929b93dd2c3a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -161,6 +161,30 @@ #size-cells = <2>; ranges; + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -172,12 +196,6 @@ alignment = <0x1000>; no-map; }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; }; }; @@ -1265,6 +1283,11 @@ ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; /* Verdin CAN_1 */ @@ -1367,6 +1390,12 @@ ""; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; +}; + /* Verdin CAN_2 */ &mcu_mcan0 { pinctrl-names = "default"; @@ -1434,6 +1463,12 @@ status = "disabled"; }; +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + /* Verdin UART_2 */ &wkup_uart0 { pinctrl-names = "default"; |