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authorSuman Anna <s-anna@ti.com>2019-06-05 11:34:31 -0500
committerTero Kristo <t-kristo@ti.com>2019-06-17 17:31:30 +0300
commit0ded541218d142e9c64c42c8a91208a4d79eb541 (patch)
tree04ce861a3f652f8ba56e0b0e35f62fffdd387ce8 /arch/arm64/boot/dts/ti
parentc67f7388a62e1de81894dfbf8c6cc296a7a86ded (diff)
arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes
Add the address space for the MCU SRAM memory to the ranges property of the cbass_mcu interconnect node so that the addresses within the mcu_sram nodes and its children can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index 50f4be2047a9..fff3ea7cc027 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -71,6 +71,7 @@
/* MCUSS Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
@@ -82,6 +83,7 @@
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */