diff options
author | Roger Quadros <rogerq@ti.com> | 2019-01-11 11:44:15 +0200 |
---|---|---|
committer | Tero Kristo <t-kristo@ti.com> | 2019-02-15 10:08:46 +0200 |
commit | 42d712a74d0911516c3dcaf64b5ed831fa4cace3 (patch) | |
tree | 19eb400110a375db8c4dfc417475fb4bf2b8601f /arch/arm64/boot/dts/ti | |
parent | fd58466a3876ddaed2773556fef616159e5c3844 (diff) |
arm64: dts: ti: k3-am65: Add MSMC RAM node
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf0000 for SYSFW
- Upper 1MB for cache
The reserved locations are subject to change at runtime by
the bootloader.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti')
-rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 9338315b0ca9..757c839718d6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -6,6 +6,26 @@ */ &cbass_main { + msmc_ram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x0 0x70000000 0x0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x70000000 0x200000>; + + atf-sram@0 { + reg = <0x0 0x20000>; + }; + + sysfw-sram@f0000 { + reg = <0xf0000 0x10000>; + }; + + l3cache-sram@100000 { + reg = <0x100000 0x100000>; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; |