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authorFaiz Abbas <faiz_abbas@ti.com>2019-01-17 15:14:23 +0530
committerTero Kristo <t-kristo@ti.com>2019-02-01 10:18:33 +0200
commit5e00e9a240391541e389c33bc5447e0a477d3037 (patch)
tree62c41aff593d9be7e738d462b0873b560d78a5fb /arch/arm64/boot/dts/ti
parentbfeffd155283772bbe78c6a05dec7c0128ee500c (diff)
arm64: dts: ti: k3-am654: Add Support for eMMC host controller
Add support for the Secure Digital Host Controller Interface (SDHCI) present on TI's AM654 SOCs. It is compatible with eMMC5.1 Host Specifications. Enable only upto HS200 speed mode. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am65-main.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 272cf8fc8d30..9338315b0ca9 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -191,4 +191,18 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ sdhci0: sdhci@4f80000 {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
+ power-domains = <&k3_pds 47>;
+ clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ };
};