diff options
| author | Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 2017-02-06 11:51:00 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-21 14:07:30 +0200 |
| commit | e31b7bb8e21ed9308b09926b96f5b896bc014973 (patch) | |
| tree | d9fa577a2f610dff75d071b40afb4a87985dd777 /arch/arm64/boot/dts/xilinx | |
| parent | 1e4e25c8ae8f05ab8634ade3b848a4c1d95cef53 (diff) | |
arm64: zynqmp: Add operating points
Adding operating-points-v2 for zynqmp.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 8e6cf0cf3a69..50636e098724 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -24,6 +24,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; + operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -33,6 +34,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -41,6 +43,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -49,6 +52,7 @@ device_type = "cpu"; enable-method = "psci"; reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -66,6 +70,31 @@ }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <1199999988>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <599999994>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <399999996>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <299999997>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; |