diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2019-04-15 18:27:28 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:18 +0800 |
commit | 5f96d0fe49c0159f60e6e75e437e11a369027ac3 (patch) | |
tree | 0807b2e9c0c1f14c34dace180b2cd4daa4f946d0 /arch/arm64/boot/dts | |
parent | 86d846cbd4729579031114c917a4cbc0ee5da36b (diff) |
arm64: dts: imx8qxp: add the rpmsg support
Add the rpmsg support.
- Setup the rpmsg reserved memory, one is used for vring, the other one
is used for shared buffers.
- The mailbox of the lsio mu5a is used by rpmsg on imx8qxp platforms
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 8 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 9 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 |
3 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 9311fbe38e97..f4e2099417ce 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -137,6 +137,14 @@ lsio_subsys: bus@5d000000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x5d200000 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + }; + lsio_mu13: mailbox@5d280000 { compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu"; reg = <0x5d280000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index e5261241fb5c..9b654659c35c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -513,6 +513,15 @@ status = "okay"; }; +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + &usbphy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index aed217e80799..ddc253d715d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -134,6 +134,15 @@ #size-cells = <2>; ranges; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; @@ -313,6 +322,22 @@ status = "disabled"; }; + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; + }; + imx8_gpu_ss: imx8_gpu_ss { compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; cores = <&gpu_3d0>; |