diff options
author | Peng Fan <peng.fan@nxp.com> | 2019-12-24 15:30:31 +0800 |
---|---|---|
committer | Peng Fan <peng.fan@nxp.com> | 2019-12-26 18:31:40 +0800 |
commit | 71615ff80539eff43edad4b6c57387c7890e9678 (patch) | |
tree | 689dd2c670a40e6a5935d6e39eb6c71c440767d1 /arch/arm64/boot/dts | |
parent | a904ae5784cd879996288f6d20e142f58b00b83a (diff) |
MLK-23168 arm64: imx8mp: jailhouse dual linux
Add jailhouse dual linux dts. The 2nd linux use SDHC3 and UART4.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts | 159 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts | 100 |
3 files changed, 260 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a39295a8a47f..91148ebf9aed 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -39,7 +39,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \ imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk-root.dtb imx8mn-ddr4-evk-inmate.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts new file mode 100644 index 000000000000..e52ba7db96bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-inmate.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Freescale i.MX8MP EVK"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial3 = &uart4; + mmc2 = &usdhc3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + next-level-cache = <&A53_L2>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + clk_dummy: clock@7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + /* The clocks are configured by 1st OS */ + clk_400m: clock@8 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "200m"; + }; + + clk_266m: clock@9 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266000000>; + clock-output-names = "266m"; + }; + + osc_24m: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x3e000000>; + + aips3: bus@30800000 { + compatible = "simple-bus"; + reg = <0x30800000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + uart4: serial@30a60000 { + compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usdhc3: mmc@30b60000 { + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + }; + }; +}; + +&uart4 { + clocks = <&osc_24m>, + <&osc_24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&usdhc3 { + clocks = <&clk_dummy>, + <&clk_266m>, + <&clk_400m>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts new file mode 100644 index 000000000000..1b68bb20e360 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include "imx8mp-evk.dts" + +/ { + resmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +/* +&cpu_pd_wait { + /delete-property/ compatible; +}; +*/ + +&clk { + init-on-array = <IMX8MP_CLK_USDHC3_ROOT + IMX8MP_CLK_NAND_USDHC_BUS + IMX8MP_CLK_UART4_ROOT>; +}; + +/* +&{/busfreq} { + status = "disabled"; +}; +*/ + +&{/reserved-memory} { + jh_reserved: jh@fdc00000 { + no-map; + reg = <0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fda00000 { + no-map; + reg = <0 0xfda00000 0x0 0x00100000>; + }; + + ivshmem2_reserved: ivshmem2@fd900000 { + no-map; + reg = <0 0xfd900000 0x0 0x00100000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0 0xfd700000 0x0 0x00200000>; + }; + + inmate_reserved: inmate@c0000000 { + no-map; + reg = <0 0xc0000000 0x0 0x3d700000>; + }; +}; + +&iomuxc { + imx8mp-evk { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + }; +}; + +&usdhc3 { + status = "disabled"; +}; + +&uart4 { + /delete-property/ dmas; + /delete-property/ dma-names; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +&uart2 { + /* uart4 is used by the 2nd OS, so configure pin and clk */ + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; +}; |