arm64: imx8-ss-dc0.dtsi: Improve DC0 subsystem device tree

This patch improves DC0 subsystem device tree to clearly reflect it is
the first DC subsystem instance embedded in a SoC. So, some renaming
happens in imx8-ss-dc.dtsi, and finally imx8-ss-dc.dtsi is renamed to be
imx8-ss-dc0.dtsi.

Also, extract the i.MX8qxp specific compatible string, display clocks,
display ports and display-subsystem from imx8-ss-dc0.dtsi and put them
in SoC specific imx8qxp-ss-dc.dtsi.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

3 files changed, 87 insertions, 76 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
index 44c6d8cae0cc..6de96872c151 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
@@ -3,39 +3,39 @@
  * Copyright 2019 NXP
  */
 
-dc_subsys: bus@56000000 {
+dc0_subsys: bus@56000000 {
 	compatible = "simple-bus";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges = <0x56000000 0x0 0x56000000 0x300000>;
 
-	dc_cfg_clk: clock-dc-cfg {
+	dc0_cfg_clk: clock-dc-cfg {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <100000000>;
-		clock-output-names = "dc_cfg_clk";
+		clock-output-names = "dc0_cfg_clk";
 	};
 
-	dc_axi_int_clk: clock-dc-axi-int {
+	dc0_axi_int_clk: clock-dc-axi-int {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <400000000>;
-		clock-output-names = "dc_axi_int_clk";
+		clock-output-names = "dc0_axi_int_clk";
 	};
 
-	dc_axi_ext_clk: clock-dc-axi-ext {
+	dc0_axi_ext_clk: clock-dc-axi-ext {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <800000000>;
-		clock-output-names = "dc_axi_ext_clk";
+		clock-output-names = "dc0_axi_ext_clk";
 	};
 
 	dc0_dpr0_lpcg: clock-controller@56010018 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010018 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_cfg_clk>,
-			 <&dc_axi_ext_clk>;
+		clocks = <&dc0_cfg_clk>,
+			 <&dc0_axi_ext_clk>;
 		bit-offset = <16 20>;
 		clock-output-names = "dc0_dpr0_lpcg_apb_clk",
 				     "dc0_dpr0_lpcg_b_clk";
@@ -46,7 +46,7 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5601001c 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>;
+		clocks = <&dc0_axi_ext_clk>;
 		bit-offset = <0>;
 		clock-output-names = "dc0_rtram0_lpcg_clk";
 		power-domains = <&pd IMX_SC_R_DC_0>;
@@ -57,8 +57,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010020 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg0_lpcg_rtram_clk",
 				     "dc0_prg0_lpcg_apb_clk";
@@ -69,8 +69,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010024 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg1_lpcg_rtram_clk",
 				     "dc0_prg1_lpcg_apb_clk";
@@ -81,8 +81,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010028 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg2_lpcg_rtram_clk",
 				     "dc0_prg2_lpcg_apb_clk";
@@ -93,8 +93,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5601002c 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_cfg_clk>,
-			 <&dc_axi_ext_clk>;
+		clocks = <&dc0_cfg_clk>,
+			 <&dc0_axi_ext_clk>;
 		bit-offset = <16 20>;
 		clock-output-names = "dc0_dpr1_lpcg_apb_clk",
 				     "dc0_dpr1_lpcg_b_clk";
@@ -105,7 +105,7 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010030 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>;
+		clocks = <&dc0_axi_ext_clk>;
 		bit-offset = <0>;
 		clock-output-names = "dc0_rtram1_lpcg_clk";
 		power-domains = <&pd IMX_SC_R_DC_0>;
@@ -115,8 +115,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010034 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg3_lpcg_rtram_clk",
 				     "dc0_prg3_lpcg_apb_clk";
@@ -127,8 +127,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010038 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg4_lpcg_rtram_clk",
 				     "dc0_prg4_lpcg_apb_clk";
@@ -139,8 +139,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x5601003c 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg5_lpcg_rtram_clk",
 				     "dc0_prg5_lpcg_apb_clk";
@@ -151,8 +151,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010040 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg6_lpcg_rtram_clk",
 				     "dc0_prg6_lpcg_apb_clk";
@@ -163,8 +163,8 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010044 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg7_lpcg_rtram_clk",
 				     "dc0_prg7_lpcg_apb_clk";
@@ -175,15 +175,15 @@ dc_subsys: bus@56000000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x56010048 0x4>;
 		#clock-cells = <1>;
-		clocks = <&dc_axi_ext_clk>,
-			 <&dc_cfg_clk>;
+		clocks = <&dc0_axi_ext_clk>,
+			 <&dc0_cfg_clk>;
 		bit-offset = <0 16>;
 		clock-output-names = "dc0_prg8_lpcg_rtram_clk",
 				     "dc0_prg8_lpcg_apb_clk";
 		power-domains = <&pd IMX_SC_R_DC_0>;
 	};
 
-	irqsteer_dpu: irqsteer@56000000 {
+	dc0_irqsteer: irqsteer@56000000 {
 		compatible = "fsl,imx-irqsteer";
 		reg = <0x56000000 0x10000>;
 		interrupt-controller;
@@ -197,7 +197,7 @@ dc_subsys: bus@56000000 {
 			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&dc_cfg_clk>;
+		clocks = <&dc0_cfg_clk>;
 		clock-names = "ipg";
 		fsl,channel = <0>;
 		fsl,num-irqs = <512>;
@@ -207,9 +207,8 @@ dc_subsys: bus@56000000 {
 	dpu1: dpu@56180000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "fsl,imx8qxp-dpu";
 		reg = <0x56180000 0x40000>;
-		interrupt-parent = <&irqsteer_dpu>;
+		interrupt-parent = <&dc0_irqsteer>;
 		interrupts = <448>, <449>, <450>,  <64>,
 			      <65>,  <66>,  <67>,  <68>,
 			      <69>,  <70>, <193>, <194>,
@@ -270,50 +269,10 @@ dc_subsys: bus@56000000 {
 				  "framegen1_primsync_off",
 				  "framegen1_secsync_on",
 				  "framegen1_secsync_off";
-		clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
-			 <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
-			 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
-			 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
-		clock-names = "pll0", "pll1", "disp0", "disp1";
 		power-domains = <&pd IMX_SC_R_DC_0>,
 				<&pd IMX_SC_R_DC_0_PLL_0>,
 				<&pd IMX_SC_R_DC_0_PLL_1>;
 		power-domain-names = "dc", "pll0", "pll1";
 		status = "disabled";
-
-		dpu_disp0: port@0 {
-			reg = <0>;
-
-			dpu_disp0_ldb1_ch0: endpoint@0 {
-				remote-endpoint = <&ldb1_ch0>;
-			};
-
-			dpu_disp0_ldb1_ch1: endpoint@1 {
-				remote-endpoint = <&ldb1_ch1>;
-			};
-
-			dpu_disp0_mipi_dsi: endpoint@2 {
-			};
-		};
-
-		dpu_disp1: port@1 {
-			reg = <1>;
-
-			dpu_disp1_ldb2_ch0: endpoint@0 {
-				remote-endpoint = <&ldb2_ch0>;
-			};
-
-			dpu_disp1_ldb2_ch1: endpoint@1 {
-				remote-endpoint = <&ldb2_ch1>;
-			};
-
-			dpu_disp1_mipi_dsi: endpoint@2 {
-			};
-		};
-	};
-
-	display-subsystem {
-		compatible = "fsl,imx-display-subsystem";
-		ports = <&dpu_disp0>, <&dpu_disp1>;
 	};
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
new file mode 100644
index 000000000000..98530941c91d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2019 NXP
+ */
+
+&dpu1 {
+	compatible = "fsl,imx8qxp-dpu";
+	clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
+		 <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
+		 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
+		 <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
+	clock-names = "pll0", "pll1", "disp0", "disp1";
+
+	dpu_disp0: port@0 {
+		reg = <0>;
+
+		dpu_disp0_ldb1_ch0: endpoint@0 {
+			remote-endpoint = <&ldb1_ch0>;
+		};
+
+		dpu_disp0_ldb1_ch1: endpoint@1 {
+			remote-endpoint = <&ldb1_ch1>;
+		};
+
+		dpu_disp0_mipi_dsi: endpoint@2 {
+		};
+	};
+
+	dpu_disp1: port@1 {
+		reg = <1>;
+
+		dpu_disp1_ldb2_ch0: endpoint@0 {
+			remote-endpoint = <&ldb2_ch0>;
+		};
+
+		dpu_disp1_ldb2_ch1: endpoint@1 {
+			remote-endpoint = <&ldb2_ch1>;
+		};
+
+		dpu_disp1_mipi_dsi: endpoint@2 {
+		};
+	};
+};
+
+/ {
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dpu_disp0>, <&dpu_disp1>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index c17f59088a15..75e43ab3c18b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -291,7 +291,7 @@
 	/* sorted in register address */
 	#include "imx8-ss-cm40.dtsi"
 	#include "imx8-ss-vpu.dtsi"
-	#include "imx8-ss-dc.dtsi"
+	#include "imx8-ss-dc0.dtsi"
 	#include "imx8-ss-lvds.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
@@ -306,6 +306,7 @@
 #include "imx8qxp-ss-conn.dtsi"
 #include "imx8qxp-ss-lsio.dtsi"
 #include "imx8qxp-ss-img.dtsi"
+#include "imx8qxp-ss-dc.dtsi"
 
 &edma2 {
 	status = "okay";