MLK-24796-2: dts: imx8qxp: add imx_mic_intr for ep and add cma node for rc

For rc, use cma node to allocate share memory from rc ddr dynamically.
So add a new imx8qxp-mek-vop.dts file for rc.
For ep, add an imx_mic_intr node to config the power and clock of
mu8a/mu8b, which are used to generate interrupts from rc to ep.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>

5 files changed, 34 insertions, 2 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 3a812c75a02e..35834790f3a0 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -146,7 +146,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
 			  imx8qxp-lpddr4-val-lpspi.dtb imx8qxp-lpddr4-val-lpspi-slave.dtb \
 			  imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \
 			  imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \
-			  imx8qxp-lpddr4-val-mlb.dtb
+			  imx8qxp-lpddr4-val-mlb.dtb imx8qxp-mek-vop.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \
 			  imx8qxp-mek-inmate.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index f406f6adce31..ff196f39949c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -163,6 +163,16 @@ lsio_subsys: bus@5d000000 {
 		power-domains = <&pd IMX_SC_R_MU_5A>;
 	};
 
+	lsio_mu8: mic_intr@5d230000 {
+		compatible = "fsl,imx-mic-intr";
+		reg = <0x5d230000 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		/* Also enable MU8B pd since MIC host need touch it's registers */
+		power-domains = <&pd IMX_SC_R_MU_8A>, <&pd IMX_SC_R_MU_8B>;
+		power-domain-names = "pd_a", "pd_b";
+		status = "disabled";
+	};
+
 	lsio_mu13: mailbox@5d280000 {
 		compatible = "fsl,imx8-mu-dsp", "fsl,imx6sx-mu";
 		reg = <0x5d280000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts
index 3651ec1d37a4..e259b929475c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-pcie-ep.dts
@@ -11,6 +11,11 @@
 	status = "disabled";
 };
 
+&lsio_mu8{
+	doorbell-reg = <0x5d2c0000 0x10000>;
+	status = "okay";
+};
+
 &pcieb_ep{
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcieb>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts
new file mode 100644
index 000000000000..1e7255a679bd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-vop.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-mek.dts"
+
+&resmem {
+	fsl,imx_mic {
+		compatible = "shared-dma-pool";
+		reusable;
+		size = <0 0x2000000>;
+		alloc-ranges = <0 0xf8000000 0 0x2000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi
index 3af1dae5207d..586eb4a172dc 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-mek.dtsi
@@ -81,7 +81,7 @@
 		};
 	};
 
-	reserved-memory {
+	resmem: reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;