diff options
author | Peng Fan <peng.fan@nxp.com> | 2019-12-17 11:06:12 +0800 |
---|---|---|
committer | Peng Fan <peng.fan@nxp.com> | 2019-12-17 17:18:22 +0800 |
commit | cbb61c1b75aefa334c1860246d69dcb315d412dc (patch) | |
tree | 9f01ec36f3e674e1efcfa1acbb8fcf01530551a1 /arch/arm64/boot/dts | |
parent | 7ff8df421e4c60ccc30063b7f9d1843b64ce01f2 (diff) |
LF-496-4 arm64: dts: add i.MX8QXP inmate/root dts
Add i.MX8QXP inmate/root dts.
Use the following command to boot the 2nd linux, the lpuart2 is in base
board.
jailhouse cell linux imx8qxp-linux-demo.cell Image -d
imx8qxp-mek-inmate.dtb -c "clk_ignore_unused console=ttyLP2,115200
earlycon=lpuart32,mmio32,0x5a060010,115200 cma=32MB root=/dev/mmcblk0p2
rootwait rw"
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts | 250 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts | 98 |
3 files changed, 350 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 173cd5736f26..d7f6c0259061 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -81,7 +81,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640 imx8qxp-lpddr4-val-spdif.dtb imx8qxp-lpddr4-val-gpmi-nand.dtb imx8dxp-lpddr4-val.dtb \ imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ imx8qxp-lpddr4-val-mlb.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ + imx8qxp-mek-inmate.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \ s32v234-sbc.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts new file mode 100644 index 000000000000..8db8a086790a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-inmate.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include <dt-bindings/clock/imx8-clock.h> +#include <dt-bindings/firmware/imx/rsrc.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pads-imx8qxp.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + model = "Freescale i.MX8QXP MEK Inmate"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + interrupt-parent = <&gic>; + #address-cells = <0x2>; + #size-cells = <0x2>; + + aliases { + mmc0 = &usdhc1; + serial2 = &lpuart2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + enable-method = "psci"; + reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3", + "gip3"; + mboxes = <&lsio_mu2 0 0 + &lsio_mu2 0 1 + &lsio_mu2 0 2 + &lsio_mu2 0 3 + &lsio_mu2 1 0 + &lsio_mu2 1 1 + &lsio_mu2 1 2 + &lsio_mu2 1 3 + &lsio_mu2 3 3>; + + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + + clk: clock-controller { + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; + #clock-cells = <2>; + clocks = <&xtal32k &xtal24m>; + clock-names = "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + soc { + compatible = "fsl,imx8qxp-soc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ + clock-frequency = <8333333>; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + xtal32k: clock-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xtal_24MHz"; + }; + + pci@fd700000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + reg = <0x0 0xfd700000 0x0 0x100000>; + ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>; + }; + + /* For early console */ + serial@5a060000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + }; + + #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" +}; + +#include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" + +&edma0 { + status = "disabled"; +}; + +&edma1 { + status = "disabled"; +}; + +&acm { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&lsio_mu1 { + status = "disabled"; +}; + +&lsio_mu2 { + status = "okay"; +}; + +&lsio_gpio0 { + status = "disabled"; +}; + +&lsio_gpio1 { + status = "disabled"; +}; + +&lsio_gpio2 { + status = "disabled"; +}; + +&lsio_gpio3 { + status = "disabled"; +}; + +&lsio_gpio4 { + status = "disabled"; +}; + +&lsio_gpio5 { + status = "disabled"; +}; + +&lsio_gpio6 { + status = "disabled"; +}; + +&lsio_gpio7 { + status = "disabled"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; + /delete-property/ dma-names; + /delete-property/ dmas; +}; + +/delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts new file mode 100644 index 000000000000..5f4ee5adbec8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-root.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright NXP 2019 + +#include "imx8qxp-mek-rpmsg.dts" + +/ { + domu { + /* + * There are 5 MUs, 0A is used by root cell, 1A is used + * by ATF, so for non-root cell, 2A/3A/4A could be used. + * SC_R_MU_0A + * SC_R_MU_1A + * SC_R_MU_2A + * SC_R_MU_3A + * SC_R_MU_4A + * The rsrcs and pads will be configured by uboot scu_rm cmd + */ + #address-cells = <1>; + #size-cells = <0>; + doma { + /* + * This is not for domu, this is just reuse + * the method for jailhouse inmate non root cell + * Linux. + */ + compatible = "xen,domu"; + /* + * The reg property will be updated by U-Boot to + * reflect the partition id. + */ + reg = <0>; + init_on_rsrcs = < + IMX_SC_R_MU_2A + >; + rsrcs = < + IMX_SC_R_SDHC_0 + IMX_SC_R_UART_2 + IMX_SC_R_MU_2A + >; + pads = < + /* emmc */ + IMX8QXP_EMMC0_CLK + IMX8QXP_EMMC0_CMD + IMX8QXP_EMMC0_DATA0 + IMX8QXP_EMMC0_DATA1 + IMX8QXP_EMMC0_DATA2 + IMX8QXP_EMMC0_DATA3 + IMX8QXP_EMMC0_DATA4 + IMX8QXP_EMMC0_DATA5 + IMX8QXP_EMMC0_DATA6 + IMX8QXP_EMMC0_DATA7 + IMX8QXP_EMMC0_STROBE + /* lpuart2 */ + IMX8QXP_UART2_TX + IMX8QXP_UART2_RX + >; + }; + }; + +}; + +&{/reserved-memory} { + + jh_reserved: jh@fdc00000 { + no-map; + reg = <0x0 0xfdc00000 0x0 0x400000>; + }; + + loader_reserved: loader@fdb00000 { + no-map; + reg = <0x0 0xfdb00000 0x0 0x00100000>; + }; + + ivshmem_reserved: ivshmem@fd900000 { + no-map; + reg = <0x0 0xfd900000 0x0 0x00200000>; + }; + + pci_reserved: pci@fd700000 { + no-map; + reg = <0x0 0xfd700000 0x0 0x00200000>; + }; + + /* Decrease if no need such big memory */ + inmate_reserved: inmate@df7000000 { + no-map; + reg = <0x0 0xdf700000 0x0 0x1e000000>; + }; +}; + +&usdhc1 { + /delete-property/ compatible; +}; + +&lpuart2 { + /* Let inmate linux use this for console */ + status = "disabled"; +}; |