MLK-19003-4 ARM64: dts: introduce i.MX8QM root/inmate dts

The two dts are for Jailhouse root cell and non-root linux cell.

root cell use SDHC1/UART0, non root cell use SDHC0/UART2.
UART2 is on base board with RS232 connected.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>

3 files changed, 400 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 1c95eb6e86fe..a331430b9bec 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -19,6 +19,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
 				 fsl-imx8qm-mek-jdi-wuxga-lvds1-panel.dtb \
 				 fsl-imx8qm-mek-dom0.dtb \
 				 fsl-imx8qm-mek-domu.dtb \
+				 fsl-imx8qm-mek-root.dtb \
+				 fsl-imx8qm-mek-inmate.dtb \
 				 fsl-imx8qm-lpddr4-arm2-dp.dtb \
 				 fsl-imx8qm-lpddr4-arm2-8cam.dtb \
 				 fsl-imx8qm-lpddr4-arm2-it6263-dual-channel.dtb \
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts
new file mode 100644
index 000000000000..87da05ecb454
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-inmate.dts
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca35.dtsi"
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	model = "Freescale i.MX8QM MEK";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+	interrupt-parent = <&gic>;
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	aliases {
+		mmc0 = &usdhc1;
+		serial2 = &lpuart2;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			enable-method = "psci";
+			reg = <0x0 0x3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8333333>;
+	};
+
+	clk: clk {
+		compatible = "fsl,imx8qm-clk";
+		#clock-cells = <1>;
+	};
+
+	iomuxc: iomuxc {
+		compatible = "fsl,imx8qm-iomuxc";
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	imx8qx-pm {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pd_conn: PD_CONN {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_LAST>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_conn_sdch0: PD_CONN_SDHC_0 {
+				reg = <SC_R_SDHC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+		};
+
+		pd_dma: PD_DMA {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_LAST>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dma_lpuart2: PD_DMA_UART2 {
+				reg = <SC_R_UART_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <347>;
+
+				pd_dma0_chan16: PD_UART2_RX {
+					reg = <SC_R_DMA_0_CH16>;
+					power-domains =<&pd_dma_lpuart2>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan17: PD_UART2_TX {
+						reg = <SC_R_DMA_0_CH17>;
+						power-domains =<&pd_dma0_chan16>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+		};
+	};
+
+	mu2: mu@5d1d0000 {
+		compatible = "fsl,imx8-mu";
+		reg = <0x0 0x5d1d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,scu_ap_mu_id = <0>;
+		status = "okay";
+	};
+
+	pci@ff700000 {
+		compatible = "pci-host-ecam-generic";
+		device_type = "pci";
+		bus-range = <0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+		reg = <0x0 0xff700000 0x0 0x100000>;
+		ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+	};
+
+	usdhc1: usdhc@5b010000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b010000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
+			<&clk IMX8QM_SDHC0_CLK>,
+			<&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
+		assigned-clock-rates = <400000000>;
+		power-domains = <&pd_conn_sdch0>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		/*iommus = <&smmu 0x11 0x7f80>;*/
+		status = "disabled";
+	};
+
+	/* For early console */
+	lpuart0: serial@5a060000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a060000 0x0 0x1000>;
+	};
+
+	lpuart2: serial@5a080000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a080000 0x0 0x1000>;
+		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_UART2_CLK>,
+			<&clk IMX8QM_UART2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma0_chan17>;
+		/*
+		 * dma-names = "tx","rx";
+		 * dmas = <&edma0 17 0 0>,
+		 * 	<&edma0 16 0 1>;
+		 */
+		status = "disabled";
+	};
+};
+
+&iomuxc {
+	imx8qxp-mek {
+		pinctrl_lpuart2: lpuart2grp {
+			fsl,pins = <
+				SC_P_UART0_RTS_B_DMA_UART2_RX		0x06000020
+				SC_P_UART0_CTS_B_DMA_UART2_TX		0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+	};
+};
+
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts
new file mode 100644
index 000000000000..98ca22a3a2c4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-root.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qm-mek.dts"
+
+/ {
+	domu {
+		/*
+		 * There are 5 MUs, 0A is used by root cell, 1A is used
+		 * by ATF, so for non-root cell, 2A/3A/4A could be used.
+		 * SC_R_MU_0A
+		 * SC_R_MU_1A
+		 * SC_R_MU_2A
+		 * SC_R_MU_3A
+		 * SC_R_MU_4A
+		 * The rsrcs and pads will be configured by uboot scu_rm cmd
+		 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		doma {
+			/*
+			 * This is not for domu, this is just reuse
+			 * the method for jailhouse inmate non root cell
+			 * Linux.
+			 */
+			compatible = "xen,domu";
+			/*
+			 * The reg property will be updated by U-Boot to
+			 * reflect the partition id.
+			 */
+			reg = <0>;
+			init_on_rsrcs = <
+				SC_R_MU_2A
+			>;
+			rsrcs = <
+				SC_R_SDHC_0
+				SC_R_DMA_0_CH16
+				SC_R_DMA_0_CH17
+				SC_R_UART_2
+				SC_R_MU_2A
+			>;
+			pads = <
+				/* emmc */
+				SC_P_EMMC0_CLK
+				SC_P_EMMC0_CMD
+				SC_P_EMMC0_DATA0
+				SC_P_EMMC0_DATA1
+				SC_P_EMMC0_DATA2
+				SC_P_EMMC0_DATA3
+				SC_P_EMMC0_DATA4
+				SC_P_EMMC0_DATA5
+				SC_P_EMMC0_DATA6
+				SC_P_EMMC0_DATA7
+				SC_P_EMMC0_STROBE
+				SC_P_EMMC0_RESET_B
+				/* lpuart2 */
+				SC_P_UART0_RTS_B
+				SC_P_UART0_CTS_B
+			>;
+		};
+	};
+
+};
+
+&{/reserved-memory} {
+
+	jh_reserved: jh@0xffc00000 {
+		no-map;
+		reg = <0x0 0xffc00000 0x0 0x400000>;
+	};
+
+	loader_reserved: loader@0xffb00000 {
+		no-map;
+		reg = <0x0 0xffb00000 0x0 0x00100000>;
+	};
+
+	ivshmem_reserved: ivshmem@0xff900000 {
+		no-map;
+		reg = <0x0 0xff900000 0x0 0x00200000>;
+	};
+
+	pci_reserved: pci@0xff700000 {
+		no-map;
+		reg = <0x0 0xff700000 0x0 0x00200000>;
+	};
+
+	/* Decrease if no need such big memory */
+	inmate_reserved: inmate@0xdf7000000 {
+		no-map;
+		reg = <0x0 0xdf700000 0x0 0x20000000>;
+	};
+};
+
+&usdhc1 {
+	/delete-property/ compatible;
+	/delete-property/ iommus;
+};
+
+&lpuart2 {
+	/* Let inmate linux use this for console */
+	status = "disabled";
+};