diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2019-08-30 11:25:13 +0200 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2019-08-30 11:25:13 +0200 |
| commit | 486161489f49d71f5fbf10f477d5063c2ab96b1d (patch) | |
| tree | 71404e96bc02b13881cd90ecb244579eb19f9098 /arch/arm64/boot | |
| parent | e43e3a26e1b74af86ad80dfdfc3d7b6672d9a676 (diff) | |
ARM64: dts: imx8qm-apalis: use low-drive for SD pins
This commit makes sure to use low-drive mode on all sd pins as
suggested by our hardware team.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index de43ad6212f4..902677aed8c3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -871,27 +871,27 @@ pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < - SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 - SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 - SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 - SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 - SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 - SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 /* On-module PMIC use */ - SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < - SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 - SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 - SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 - SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 - SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 - SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 /* On-module PMIC use */ - SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 >; }; |