diff options
author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2019-10-30 14:37:11 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:08:51 +0800 |
commit | 0e1ccc89bbaab36bfe96431aafecdb7357a24e81 (patch) | |
tree | 257dbc568888a3bb8ce76a1847fbfe77870d47a8 /arch/arm64/boot | |
parent | 355e11eebfaabc4c9a8c33da63f541168bd0f802 (diff) |
arm64: dts: imx8qxp-lpddr4-val: support audio sound card
Add support audio sound card (ESAI/ASRC/AMIX/CS42888/MQS)
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts | 60 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts | 56 | ||||
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts | 164 |
4 files changed, 282 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ec16b7dfe1bf..49b92fa18534 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -44,4 +44,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \ imx8qxp-mek-enet2.dtb imx8qxp-mek-enet2-tja1100.dtb imx8qxp-mek-sof.dtb \ imx8qxp-mek-rpmsg.dtb \ - imx8qxp-lpddr4-val.dtb + imx8qxp-lpddr4-val.dtb imx8qxp-lpddr4-val-mqs.dtb \ + imx8qxp-lpddr4-val-spdif.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts new file mode 100644 index 000000000000..dacf725d2487 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-mqs.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-mqs { + compatible = "fsl,imx8qxp-lpddr4-arm2-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; + asrc-controller = <&asrc1>; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_mqs: mqsgrp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_MQS_L 0xc6000061 + IMX8QXP_SPDIF0_RX_ADMA_MQS_R 0xc6000061 + >; + }; +}; + +&mqs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts new file mode 100644 index 000000000000..81ec0d0e9b98 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val-spdif.dts @@ -0,0 +1,56 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx8qxp-lpddr4-val.dts" + +/ { + sound-cs42888 { + status = "disabled"; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; +}; + +&iomuxc { + pinctrl_spdif0: spdif0grp { + fsl,pins = < + IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX 0xc6000040 + IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX 0xc6000040 + >; + }; +}; + +&esai0 { + status = "disabled"; +}; + +&spdif0 { + compatible = "fsl,imx8qm-spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&spdif0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts index 61282f800721..53a79434b63f 100755 --- a/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-lpddr4-val.dts @@ -85,6 +85,77 @@ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_audio: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound-cs42888 { + compatible = "fsl,imx8qm-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai0>; + audio-codec = <&cs42888>; + asrc-controller = <&asrc0>; + status = "okay"; + }; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div1_lpcg 0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <24576000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; }; &lpuart0 { @@ -176,9 +247,95 @@ }; }; +&irqsteer_csi0 { + status = "okay"; +}; + +&i2c_mipi_csi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_mipi_csi0>; + clock-frequency = <100000>; + status = "okay"; + + cs42888: cs42888@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; + power-domains = <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>; + power-domain-names = "pd_mclk_out_0", + "pd_audio_clk_0", + "pd_audio_clk_1", + "pd_audio_clk_0", + "pd_audio_clk_1"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &iomuxc { pinctrl-names = "default"; + pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 + IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0xc6000040 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 @@ -200,6 +357,13 @@ >; }; + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 |