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authorKrzysztof Kozlowski <krzk@kernel.org>2019-04-15 20:34:39 +0200
committerKrzysztof Kozlowski <krzk@kernel.org>2019-04-24 19:57:15 +0200
commit179a2802ac0f9a8e7ac7a5be83d1a39b03f27056 (patch)
treee2e509f8dab75ef10c56f81a63b3fd68cfa70171 /arch/arm64/boot
parent77fc46976e0bfcd78d30fb4c9f0169752b4339c9 (diff)
arm64: dts: exynos: Move pmu and timer nodes out of soc
The ARM PMU and ARM architected timer nodes are part of ARM CPU design therefore they should not be inside the soc node. This also fixes DTC W=1 warnings like: arch/arm64/boot/dts/exynos/exynos7.dtsi:472.11-480.5: Warning (simple_bus_reg): /soc/arm-pmu: missing or empty reg/ranges property arch/arm64/boot/dts/exynos/exynos7.dtsi:482.9-492.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi36
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7.dtsi44
2 files changed, 40 insertions, 40 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 41ecbc49c61e..62cedf9855cf 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -23,6 +23,24 @@
interrupt-parent = <&gic>;
+ arm_a53_pmu {
+ compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ arm_a57_pmu {
+ compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -237,24 +255,6 @@
#size-cells = <1>;
ranges;
- arm_a53_pmu {
- compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- arm_a57_pmu {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
- };
-
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 967558a93d82..f83ad4c491f2 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -28,6 +28,16 @@
tmuctrl0 = &tmuctrl_0;
};
+ arm-pmu {
+ compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
+ <&cpu_atlas2>, <&cpu_atlas3>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -469,28 +479,6 @@
status = "disabled";
};
- arm-pmu {
- compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
- <&cpu_atlas2>, <&cpu_atlas3>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
pmu_system_controller: system-controller@105c0000 {
compatible = "samsung,exynos7-pmu", "syscon";
reg = <0x105c0000 0x5000>;
@@ -635,6 +623,18 @@
};
};
};
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
};
#include "exynos7-pinctrl.dtsi"