summaryrefslogtreecommitdiff
path: root/arch/arm64/boot
diff options
context:
space:
mode:
authorKatsuhiro Suzuki <katsuhiro@katsuster.net>2019-04-07 00:35:57 +0900
committerHeiko Stuebner <heiko@sntech.de>2019-04-11 14:41:34 +0200
commit40a0dd4253c03e7ec21dd38f25901486d34b01c7 (patch)
tree1c14b3c6861a5164f8b43e1fdb67b82cce6047c3 /arch/arm64/boot
parentd64420e816059661e70db31d891f38e79f483080 (diff)
arm64: dts: rockchip: fix cts, rts pin assign of UART3 for rk3399
This patch fixes pin assign of cts and rts signal of UART3. Currently GPIO3_C2 and C3 pins are assigned but TRM says that GPIO3_C0 and C1 are correct. Refer: RK3399 TRM v1.4 - Table 19-1 UART Interface Description Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f54c855f8cdf..196ac9b78076 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2543,12 +2543,12 @@
uart3_cts: uart3-cts {
rockchip,pins =
- <3 RK_PC2 2 &pcfg_pull_none>;
+ <3 RK_PC0 2 &pcfg_pull_none>;
};
uart3_rts: uart3-rts {
rockchip,pins =
- <3 RK_PC3 2 &pcfg_pull_none>;
+ <3 RK_PC1 2 &pcfg_pull_none>;
};
};