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authorPeng Fan <peng.fan@nxp.com>2019-10-31 16:42:58 +0800
committerDong Aisheng <aisheng.dong@nxp.com>2019-11-25 16:08:54 +0800
commit510ef26e4ea282544eb2bea5daa15b49f958eab2 (patch)
treecd8fd25d3c9b7c6efce5a24edf4b9340a255f019 /arch/arm64/boot
parent805cf7d9ed98ebd6962a293b889505f9b275076f (diff)
arm64: dts: imx8qm: add smmu
Add smmu node, enable smmu for usdhc/fec/usb/sata Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi13
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi1
-rwxr-xr-xarch/arm64/boot/dts/freescale/imx8qm.dtsi17
3 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
index b566b813225d..00ebdc6fc875 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
@@ -6,16 +6,29 @@
&fec1 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
};
&fec2 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
+ iommus = <&smmu 0x12 0x7f80>;
};
&usdhc1 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
};
&usdhc2 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
+};
+
+&usdhc3 {
+ compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc";
+ iommus = <&smmu 0x11 0x7f80>;
+};
+
+&usbotg3 {
+ iommus = <&smmu 0x4 0x7f80>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index 4cd5a17e2ab6..7dce914110e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -161,6 +161,7 @@
<&pd IMX_SC_R_SERDES_0>,
<&pd IMX_SC_R_SERDES_1>,
<&pd IMX_SC_R_HSIO_GPIO>;
+ iommus = <&smmu 0x13 0x7f80>;
status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 85cf87800faa..d435042efc95 100755
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -231,6 +231,23 @@
clock-output-names = "xtal_24MHz";
};
+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3",