diff options
author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-15 19:33:22 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:52 +0800 |
commit | 584d6494721a02984462cbf45df1d8ca84d8d7db (patch) | |
tree | 9861206f1d555fbb62e8827ca46c980e907339c2 /arch/arm64/boot | |
parent | df244316e4feed2a1e07c5e5c3e17ff990ec9b71 (diff) |
arm64: dts: imx8: switch to new lpcg clock binding
switch to new lpcg clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 35 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 62 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 14 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 4 |
6 files changed, 56 insertions, 67 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 88f52e5a62e4..9393e9bc5b94 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -19,13 +19,6 @@ adma_subsys: bus@59000000 { clock-output-names = "dma_ipg_clk"; }; - /* LPCG clocks */ - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - edma0: dma-controller@591F0000 { compatible = "fsl,imx8qm-edma"; reg = <0x59200000 0x10000>, /* asrc0 */ @@ -165,8 +158,7 @@ adma_subsys: bus@59000000 { reg = <0x5a060000 0x1000>; interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clocks = <&uart0_lpcg 1>, <&uart0_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_ADMA_UART0_CLK>; assigned-clock-rates = <80000000>; @@ -178,8 +170,7 @@ adma_subsys: bus@59000000 { reg = <0x5a070000 0x1000>; interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; + clocks = <&uart1_lpcg 1>, <&uart1_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_ADMA_UART1_CLK>; assigned-clock-rates = <80000000>; @@ -197,8 +188,7 @@ adma_subsys: bus@59000000 { reg = <0x5a080000 0x1000>; interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; + clocks = <&uart2_lpcg 1>, <&uart2_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_ADMA_UART2_CLK>; assigned-clock-rates = <80000000>; @@ -216,8 +206,7 @@ adma_subsys: bus@59000000 { reg = <0x5a090000 0x1000>; interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; + clocks = <&uart3_lpcg 1>, <&uart3_lpcg 0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_ADMA_UART3_CLK>; assigned-clock-rates = <80000000>; @@ -232,6 +221,7 @@ adma_subsys: bus@59000000 { }; uart0_lpcg: clock-controller@5a460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, @@ -243,6 +233,7 @@ adma_subsys: bus@59000000 { }; uart1_lpcg: clock-controller@5a470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, @@ -254,6 +245,7 @@ adma_subsys: bus@59000000 { }; uart2_lpcg: clock-controller@5a480000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a480000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, @@ -265,6 +257,7 @@ adma_subsys: bus@59000000 { }; uart3_lpcg: clock-controller@5a490000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a490000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, @@ -279,7 +272,7 @@ adma_subsys: bus@59000000 { reg = <0x5a800000 0x4000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clocks = <&i2c0_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -291,7 +284,7 @@ adma_subsys: bus@59000000 { reg = <0x5a810000 0x4000>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clocks = <&i2c1_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -303,7 +296,7 @@ adma_subsys: bus@59000000 { reg = <0x5a820000 0x4000>; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clocks = <&i2c2_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -315,7 +308,7 @@ adma_subsys: bus@59000000 { reg = <0x5a830000 0x4000>; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clocks = <&i2c3_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -720,6 +713,7 @@ adma_subsys: bus@59000000 { }; i2c0_lpcg: clock-controller@5ac00000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, @@ -731,6 +725,7 @@ adma_subsys: bus@59000000 { }; i2c1_lpcg: clock-controller@5ac10000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac10000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, @@ -742,6 +737,7 @@ adma_subsys: bus@59000000 { }; i2c2_lpcg: clock-controller@5ac20000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac20000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, @@ -753,6 +749,7 @@ adma_subsys: bus@59000000 { }; i2c3_lpcg: clock-controller@5ac30000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac30000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 1339139a4555..8546456afa36 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -68,9 +68,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -84,9 +84,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -100,9 +100,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -118,11 +118,11 @@ conn_subsys: bus@5b000000 { <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_RGMII_TXC_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TIMER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TXC_SAMPLING_CLK>; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&enet0_lpcg 3>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, <&clk IMX_CONN_ENET0_REF_DIV>; @@ -139,11 +139,11 @@ conn_subsys: bus@5b000000 { <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TIMER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK>; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&enet1_lpcg 3>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, <&clk IMX_CONN_ENET1_REF_DIV>; @@ -155,12 +155,8 @@ conn_subsys: bus@5b000000 { }; /* LPCG clocks */ - conn_lpcg: clock-controller-legacy@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b200000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, @@ -173,6 +169,7 @@ conn_subsys: bus@5b000000 { }; sdhc1_lpcg: clock-controller@5b210000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b210000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, @@ -185,6 +182,7 @@ conn_subsys: bus@5b000000 { }; sdhc2_lpcg: clock-controller@5b220000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b220000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, @@ -197,30 +195,34 @@ conn_subsys: bus@5b000000 { }; enet0_lpcg: clock-controller@5b230000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b230000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; - bit-offset = <0 4 8 16 20>; - clock-output-names = "enet0_ipg_root_clk", - "enet0_tx_clk", + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet0_timer_clk", + "enet0_txc_sampling_clk", "enet0_ahb_clk", + "enet0_rgmii_txc_clk", "enet0_ipg_clk", "enet0_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_0>; }; enet1_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b240000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; - bit-offset = <0 4 8 16 20>; - clock-output-names = "enet1_ipg_root_clk", - "enet1_tx_clk", + bit-offset = <0 4 8 12 16 20>; + clock-output-names = "enet1_timer_clk", + "enet1_txc_sampling_clk", "enet1_ahb_clk", + "enet1_rgmii_txc_clk", "enet1_ipg_clk", "enet1_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 40a9a2c862d9..7eac43f1f655 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -173,13 +173,8 @@ lsio_subsys: bus@5d000000 { }; /* LPCG clocks */ - lsio_lpcg: clock-controller-legacy@5d400000 { - compatible = "fsl,imx8qm-lpcg-lsio", "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - pwm0_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d400000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, @@ -197,6 +192,7 @@ lsio_subsys: bus@5d000000 { }; pwm1_lpcg: clock-controller@5d410000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d410000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, @@ -214,6 +210,7 @@ lsio_subsys: bus@5d000000 { }; pwm2_lpcg: clock-controller@5d420000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d420000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, @@ -231,6 +228,7 @@ lsio_subsys: bus@5d000000 { }; pwm3_lpcg: clock-controller@5d430000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d430000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, @@ -248,6 +246,7 @@ lsio_subsys: bus@5d000000 { }; pwm4_lpcg: clock-controller@5d440000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d440000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, @@ -265,6 +264,7 @@ lsio_subsys: bus@5d000000 { }; pwm5_lpcg: clock-controller@5d450000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d450000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, @@ -282,6 +282,7 @@ lsio_subsys: bus@5d000000 { }; pwm6_lpcg: clock-controller@5d460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, @@ -299,6 +300,7 @@ lsio_subsys: bus@5d000000 { }; pwm7_lpcg: clock-controller@5d470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 5809324de8df..c80303d5cc78 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ -&adma_lpcg { - compatible = "fsl,imx8qxp-lpcg-adma"; -}; - &adma_lpuart0 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index ea0cd518680b..8dd22bdd72c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ -&conn_lpcg { - compatible = "fsl,imx8qxp-lpcg-conn"; -}; - &usdhc1 { compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 57979dc4ca77..48ffdb001a33 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -55,7 +55,3 @@ &lsio_mu4 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; - -&lsio_lpcg { - compatible = "fsl,imx8qxp-lpcg-lsio"; -}; |