arm64: imx8-ss-dc0/1.dtsi: Add dc0/1_prg1/2 and dc0/1_dpr1_channel1/2 support

This patch adds dc0/1_prg1/2 and dc0/1_dpr1_channel1/2 support for
DC0/1 subsystems.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

2 files changed, 96 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
index 5ccac755176c..ccb15d0dbc75 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi
@@ -215,6 +215,54 @@ dc0_subsys: bus@56000000 {
 		power-domains = <&pd IMX_SC_R_DC_0>;
 	};
 
+	dc0_prg1: prg@56040000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x56040000 0x10000>;
+		clocks = <&dc0_prg0_lpcg 0>,
+			 <&dc0_prg0_lpcg 1>;
+		clock-names = "rtram", "apb";
+		power-domains = <&pd IMX_SC_R_DC_0>;
+		status = "disabled";
+	};
+
+	dc0_prg2: prg@56050000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x56050000 0x10000>;
+		clocks = <&dc0_prg1_lpcg 0>,
+			 <&dc0_prg1_lpcg 1>;
+		clock-names = "rtram", "apb";
+		power-domains = <&pd IMX_SC_R_DC_0>;
+		status = "disabled";
+	};
+
+	dc0_dpr1_channel1: dpr-channel@560d0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x560d0000 0x10000>;
+		fsl,sc-resource = <IMX_SC_R_DC_0_BLIT0>;
+		fsl,prgs = <&dc0_prg1>;
+		clocks = <&dc0_dpr0_lpcg 0>,
+			 <&dc0_dpr0_lpcg 1>,
+			 <&dc0_rtram0_lpcg 0>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd IMX_SC_R_DC_0>;
+		status = "disabled";
+	};
+
+	dc0_dpr1_channel2: dpr-channel@560e0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x560e0000 0x10000>;
+		fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
+		fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
+		clocks = <&dc0_dpr0_lpcg 0>,
+			 <&dc0_dpr0_lpcg 1>,
+			 <&dc0_rtram0_lpcg 0>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd IMX_SC_R_DC_0>;
+		status = "disabled";
+	};
+
 	dpu1: dpu@56180000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
index 375d3f9c8fc3..49da21e1356f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi
@@ -216,6 +216,54 @@ dc1_subsys: bus@57000000 {
 		power-domains = <&pd IMX_SC_R_DC_1>;
 	};
 
+	dc1_prg1: prg@57040000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x57040000 0x10000>;
+		clocks = <&dc1_prg0_lpcg 0>,
+			 <&dc1_prg0_lpcg 1>;
+		clock-names = "rtram", "apb";
+		power-domains = <&pd IMX_SC_R_DC_1>;
+		status = "disabled";
+	};
+
+	dc1_prg2: prg@57050000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x57050000 0x10000>;
+		clocks = <&dc1_prg1_lpcg 0>,
+			 <&dc1_prg1_lpcg 1>;
+		clock-names = "rtram", "apb";
+		power-domains = <&pd IMX_SC_R_DC_1>;
+		status = "disabled";
+	};
+
+	dc1_dpr1_channel1: dpr-channel@570d0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x570d0000 0x10000>;
+		fsl,sc-resource = <IMX_SC_R_DC_1_BLIT0>;
+		fsl,prgs = <&dc1_prg1>;
+		clocks = <&dc1_dpr0_lpcg 0>,
+			 <&dc1_dpr0_lpcg 1>,
+			 <&dc1_rtram0_lpcg 0>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd IMX_SC_R_DC_1>;
+		status = "disabled";
+	};
+
+	dc1_dpr1_channel2: dpr-channel@570e0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x570e0000 0x10000>;
+		fsl,sc-resource = <IMX_SC_R_DC_1_BLIT1>;
+		fsl,prgs = <&dc1_prg2>, <&dc1_prg1>;
+		clocks = <&dc1_dpr0_lpcg 0>,
+			 <&dc1_dpr0_lpcg 1>,
+			 <&dc1_rtram0_lpcg 0>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd IMX_SC_R_DC_1>;
+		status = "disabled";
+	};
+
 	dpu2: dpu@57180000 {
 		#address-cells = <1>;
 		#size-cells = <0>;