diff options
| author | Han Xu <han.xu@nxp.com> | 2019-11-20 14:29:38 -0600 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:10:19 +0800 |
| commit | 69456b33fae47f34b59d49c4bbf5699e7e001df0 (patch) | |
| tree | 1e656a72829a1b552ad410b2d741567eed459c79 /arch/arm64/boot | |
| parent | 1126a15315f2da3b927dd3f59d1cc7263d283a81 (diff) | |
MLK-23015: add flexspi support for iMX8MN DDR4 EVK
Add flexspi support in iMX8MN DDR4 EVK dts
Signed-off-by: Han Xu <han.xu@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 25 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 |
2 files changed, 30 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 33303778da09..3adcd2bcb88d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -133,6 +133,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + pinctrl_mipi_dsi_en: mipi_dsi_en { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 @@ -539,6 +550,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 1a196a5e401e..3f668cd6de0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -896,12 +896,13 @@ flexspi: spi@30bb0000 { #address-cells = <1>; #size-cells = <0>; - compatible = "nxp,imx8mm-flexspi"; + compatible = "nxp,imx8mm-fspi"; reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; - reg-names = "fspi_base", "fspi-mmap"; + reg-names = "fspi_base", "fspi_mmap"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_QSPI_ROOT>; - clock-names = "fspi"; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; assigned-clock-rates = <80000000>; assigned-clocks = <&clk IMX8MN_CLK_QSPI>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; |