diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-11-06 10:33:51 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:11 +0800 |
| commit | 7a34d0e8b2f6a6dcf6c8461d06604058594f2a47 (patch) | |
| tree | c75a2973235a5caffca1bfda536e77a69ea2aa0c /arch/arm64/boot | |
| parent | 414eb312b28c62be0bf7e69b55bf17f774763761 (diff) | |
arm64: dts: imx8qm: Add LPDDR4 validation board single cluster support
Add *-ca53.dtb and *-ca72.dtb to support booting up single
cluster on LPDDR4 validation board, to boot up single A72 cluster,
dedicated flash.bin needs to be used.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts | 30 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts | 30 |
3 files changed, 62 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 77fefc44c202..ae0ae4b0f7ec 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -43,7 +43,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qm-mek-hdmi.dtb imx8qm-mek-dsp.dtb \ imx8qm-lpddr4-val.dtb imx8qm-lpddr4-val-mqs.dtb \ imx8qm-lpddr4-val-spdif.dtb imx8qm-mek-ca53.dtb \ - imx8qm-mek-ca72.dtb + imx8qm-mek-ca72.dtb imx8qm-lpddr4-val-ca53.dtb \ + imx8qm-lpddr4-val-ca72.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-phantom-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts new file mode 100644 index 000000000000..53f8bad38368 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca53.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal1; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts new file mode 100644 index 000000000000..e59fd9cddd7d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-ca72.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8qm-lpddr4-val.dts" + +&thermal_zones { + /delete-node/ cpu-thermal0; + + pmic-thermal0 { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@0; + /delete-node/ cpu@1; + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; |