diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2019-12-04 19:03:59 -0600 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-11 13:58:36 +0800 |
| commit | 7ae82f64e9648cca0e3c9f59a678b80138d251e1 (patch) | |
| tree | fe3137eccf0bb05a5a74927dc0303381caef3e05 /arch/arm64/include/asm/tlbflush.h | |
| parent | faee6309301eb0e0866e7e3a0df3f7747f38bbd5 (diff) | |
LF-363 arm64: kernel: TKT340553 Errata workaround update for i.MX8QM
As per latest i.MX8QM SOC Errata, TKT340553 workaround needs to be
updated to unconditionally downgrade TLB operations and instruction
cache maintenance.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/include/asm/tlbflush.h')
| -rw-r--r-- | arch/arm64/include/asm/tlbflush.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 2220f4f92ff9..e774f7cfad2c 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -151,9 +151,9 @@ static inline void flush_tlb_mm(struct mm_struct *mm) unsigned long asid = __TLBI_VADDR(0, ASID(mm)); dsb(ishst); - if (TKT340553_SW_WORKAROUND && ASID(mm) >> 12) { + if (TKT340553_SW_WORKAROUND) { __tlbi(vmalle1is); - } else { + } else { __tlbi(aside1is, asid); __tlbi_user(aside1is, asid); } @@ -166,8 +166,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); - if (TKT340553_SW_WORKAROUND && (uaddr >> 36 || (ASID(vma->vm_mm) >> 12))) { - __tlbi(vmalle1is); + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalle1is); } else { __tlbi(vale1is, addr); __tlbi_user(vale1is, addr); @@ -212,9 +212,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, dsb(ishst); for (addr = start; addr < end; addr += stride) { - if (TKT340553_SW_WORKAROUND && (addr & mask || (ASID(vma->vm_mm) >> 12))) { - __tlbi(vmalle1is); - } else if (last_level) { + if (TKT340553_SW_WORKAROUND) { + __tlbi(vmalle1is); + } else if (last_level) { __tlbi(vale1is, addr); __tlbi_user(vale1is, addr); } else { @@ -222,6 +222,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, __tlbi_user(vae1is, addr); } } + dsb(ish); } @@ -249,8 +250,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (TKT340553_SW_WORKAROUND && addr >> 24) - __tlbi(vmalle1is); + if (TKT340553_SW_WORKAROUND) + __tlbi(vmalle1is); else __tlbi(vaale1is, addr); } @@ -267,7 +268,7 @@ static inline void __flush_tlb_kernel_pgtable(unsigned long kaddr) unsigned long addr = __TLBI_VADDR(kaddr, 0); dsb(ishst); - if (TKT340553_SW_WORKAROUND && addr >> 24) + if (TKT340553_SW_WORKAROUND) __tlbi(vmalle1is); else __tlbi(vaae1is, addr); |