diff options
| author | Nitin Garg <nitin.garg@nxp.com> | 2019-12-04 19:03:59 -0600 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2019-12-11 13:58:36 +0800 |
| commit | 7ae82f64e9648cca0e3c9f59a678b80138d251e1 (patch) | |
| tree | fe3137eccf0bb05a5a74927dc0303381caef3e05 /arch/arm64/kernel/traps.c | |
| parent | faee6309301eb0e0866e7e3a0df3f7747f38bbd5 (diff) | |
LF-363 arm64: kernel: TKT340553 Errata workaround update for i.MX8QM
As per latest i.MX8QM SOC Errata, TKT340553 workaround needs to be
updated to unconditionally downgrade TLB operations and instruction
cache maintenance.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/kernel/traps.c')
| -rw-r--r-- | arch/arm64/kernel/traps.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 34739e80211b..3661d78e93fe 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -426,6 +426,29 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) uaccess_ttbr0_disable(); \ } +#define __user_cache_maint_ivau(insn, address, res) \ + do { \ + if (address >= user_addr_max()) { \ + res = -EFAULT; \ + } else { \ + uaccess_ttbr0_enable(); \ + asm volatile ( \ + "1: " insn "\n" \ + " mov %w0, #0\n" \ + "2:\n" \ + " .pushsection .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %w0, %w2\n" \ + " b 2b\n" \ + " .popsection\n" \ + _ASM_EXTABLE(1b, 3b) \ + : "=r" (res) \ + : "r" (address), "i" (-EFAULT)); \ + uaccess_ttbr0_disable(); \ + } \ + } while (0) + +extern bool TKT340553_SW_WORKAROUND; static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) { unsigned long address; @@ -452,7 +475,10 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) __user_cache_maint("dc civac", address, ret); break; case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ - __user_cache_maint("ic ivau", address, ret); + if (TKT340553_SW_WORKAROUND) + __user_cache_maint_ivau("ic ialluis", address, ret); + else + __user_cache_maint("ic ivau", address, ret); break; default: force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc); |