diff options
author | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2020-07-06 20:17:30 +0300 |
---|---|---|
committer | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2020-07-06 20:24:05 +0300 |
commit | d6e1cff14875d6ce338c1f27afe0639ef0f97b79 (patch) | |
tree | 2449859b19a9e58abb0414700621a86f234d91d6 /arch/arm64 | |
parent | 453fdfde79e13e27030a56c7ea787e98698b0dba (diff) | |
parent | 0347fe7527d062e1762498cb5863bcd5bde0997b (diff) |
Merge branch 'imx_4.14.98_2.3.0' into toradex_4.14-2.3.x-imx
Fix conflicts after merging changes from the latest NXP branch.
Conflicts:
arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
drivers/pci/dwc/pci-imx6.c
Related-to: ELB-1306
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 9 | ||||
-rwxr-xr-x | arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts | 6 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts | 25 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 25 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 17 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts | 57 |
7 files changed, 121 insertions, 19 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index fd55fa614226..77f08d0f55a2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \ fsl-imx8qm-mek-root.dtb \ fsl-imx8qm-mek-inmate.dtb \ + fsl-imx8qm-pcieax2pciebx1.dtb \ fsl-imx8qm-lpddr4-arm2-dp.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 913f8e83707a..3aebf64eaa2b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1108,7 +1108,7 @@ }; }; - pd_hsio: hsio-power-domain { + pd_hsio: PD_HSIO { compatible = "nxp,imx8-pd"; reg = <SC_R_NONE>; #power-domain-cells = <0>; @@ -3553,8 +3553,11 @@ <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, - <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 105 4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts index 5a522e6c05fc..30dd84f67da6 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts @@ -630,8 +630,8 @@ ldo1_reg: regulator@8 { reg = <8>; regulator-compatible = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -639,7 +639,7 @@ ldo2_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts index 86e2c78e99ff..d8a516c71e22 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts @@ -613,8 +613,8 @@ ldo1_reg: regulator@8 { reg = <8>; regulator-compatible = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; regulator-boot-on; regulator-always-on; }; @@ -622,7 +622,7 @@ ldo2_reg: regulator@9 { reg = <9>; regulator-compatible = "ldo2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; @@ -966,12 +966,6 @@ }; &A53_0 { - operating-points = < - /* kHz uV */ - 1500000 1000000 - 1400000 950000 - 1200000 950000 - >; arm-supply = <&buck2_reg>; }; @@ -984,6 +978,19 @@ }; &gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index c85fd8aed9ad..71133435d2f6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -4160,8 +4160,12 @@ clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, - <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, @@ -4203,8 +4207,13 @@ clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, - <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, @@ -4230,10 +4239,18 @@ <&clk IMX8QM_HSIO_PHY_X1_PCLK>, <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_SATA_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", "phy_pclk0", "phy_pclk1", "phy_apbclk"; hsio = <&hsio>; power-domains = <&pd_sata0>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index 4c2c29695644..8634b5d1f30a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -466,6 +466,14 @@ >; }; + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + pinctrl_sim0: sim0grp { fsl,pins = < SC_P_SIM0_CLK_DMA_SIM0_CLK 0xc0000021 @@ -1138,6 +1146,15 @@ status = "okay"; }; +&pcieb { + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &intmux_cm40 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..6bac94c0b44c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + + +#include "fsl-imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = <PCIEAX2PCIEBX1> + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + power-domains = <&pd_pcie1>; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; + |