diff options
author | Liu Ying <victor.liu@nxp.com> | 2019-08-07 10:25:17 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:35 +0800 |
commit | 3649a4a793d5aeadf04956813242cd648d445c5f (patch) | |
tree | f8606869555f0d738c2735e409aa9603984dde23 /arch/arm64 | |
parent | dfe3fe9d5feb9033151ab555114771abe5884aba (diff) |
arm64: imx8qm.dtsi: Add LVDS0/1 subsystems support
This patch adds LVDS0/1 subsystems support for i.MX8qm.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 294 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qm.dtsi | 3 |
3 files changed, 301 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi index 172f7127fdca..56a63a4cfabf 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dc.dtsi @@ -20,9 +20,11 @@ reg = <1>; dpu1_disp1_ldb1_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; }; dpu1_disp1_ldb1_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; }; }; }; @@ -48,9 +50,11 @@ reg = <1>; dpu2_disp1_ldb2_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; }; dpu2_disp1_ldb2_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi new file mode 100644 index 000000000000..bec0a58a28ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds1_subsys: bus@56240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56240000 0x0 0x56240000 0x10000>; + + lvds_ipg_clk: clock-lvds-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "lvds_ipg_clk"; + }; + + lvds0_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c0_lpcg_clk", + "lvds0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + lvds0_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds0_i2c1_lpcg_clk", + "lvds0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + }; + + irqsteer_lvds0: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; + + lvds0_region: lvds_region@56240000 { + compatible = "syscon"; + reg = <0x56240000 0x10000>; + }; + + ldb1_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-phy"; + reg = <0x56241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + gpr = <&lvds0_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu1_disp1_ldb1_ch1>; + }; + }; + }; + }; + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56247000 0x4000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&lvds0_i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>; + status = "disabled"; + }; + }; + + lvds2_subsys: bus@57240000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x57240000 0x0 0x57240000 0x10000>; + + lvds1_lis_lpcg: clock-controller@57243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243000 0x4>; + #clock-cells = <1>; + clocks = <&lvds_ipg_clk>; + bit-offset = <16>; + clock-output-names = "lvds1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_i2c0_lpcg: clock-controller@57243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c0_lpcg_clk", + "lvds1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + lvds1_i2c1_lpcg: clock-controller@57243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&lvds_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "lvds1_i2c1_lpcg_clk", + "lvds1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + }; + + irqsteer_lvds1: irqsteer@57240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x57240000 0x1000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&lvds0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + }; + + lvds1_region: lvds_region@57240000 { + compatible = "syscon"; + reg = <0x57240000 0x10000>; + }; + + ldb2_phy: ldb_phy@57241000 { + compatible = "mixel,lvds-phy"; + reg = <0x57241000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + gpr = <&lvds1_region>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu2_disp1_ldb2_ch1>; + }; + }; + }; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x57247000 0x4000>; + interrupts = <9>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&lvds1_i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index f10006f082e6..9d98fcf423f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -41,6 +41,8 @@ can2 = &flexcan3; dpu0 = &dpu1; dpu1 = &dpu2; + ldb0 = &ldb1; + ldb1 = &ldb2; }; cpus { @@ -403,3 +405,4 @@ #include "imx8qm-ss-lsio.dtsi" #include "imx8qm-ss-hsio.dtsi" #include "imx8qm-ss-dc.dtsi" +#include "imx8qm-ss-lvds.dtsi" |