MLK-24334-6: arch: arm64: dts: im8dxl: add lcdif dts file

Create the LCDIF to parallel display WKS 1010WX001 specific use-case dts file.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

2 files changed, 116 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 7b27addc9603..c31539074d92 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -150,6 +150,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \
 			  imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb \
 			  imx8dxl-evk-lpspi-slave.dtb \
 			  imx8dxl-evk-pcie-ep.dtb \
+			  imx8dxl-evk-lcdif.dtb \
 			  imx8dxl-ddr3-val.dtb imx8dxl-evk-root.dtb imx8dxl-evk-inmate.dtb
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \
 			  s32v234-sbc.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts
new file mode 100644
index 000000000000..c5ade6340324
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk-lcdif.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP.
+ */
+
+#include "imx8dxl-evk.dts"
+
+/ {
+	panel {
+		compatible = "wks,101wx001";
+		blctr-gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+		pinctrl-assert-gpios = <&pca6416_1 3 GPIO_ACTIVE_LOW>,
+				       <&pca6416_1 4 GPIO_ACTIVE_LOW>,
+				       <&pca6416_1 6 GPIO_ACTIVE_LOW>,
+				       <&pca6416_1 7 GPIO_ACTIVE_LOW>,
+				       <&pca6416_1 8 GPIO_ACTIVE_LOW>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&lcdif_out>;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD  0x000514a0
+		>;
+	};
+};
+
+&sai1 {
+	status = "disabled";
+};
+
+&m2_uart1_sel {
+	status = "disabled";
+};
+
+&lpuart1 {
+	status = "disabled";
+};
+
+&cm40_lpuart {
+	status = "disabled";
+};
+
+&eqos {
+	status = "disabled";
+};
+
+&lpspi3 {
+	status = "disabled";
+};
+
+&wm8960_1 {
+	status = "disabled";
+};
+
+&wm8960_2 {
+	status = "disabled";
+};
+
+&wm8960_3 {
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl_lcdif: lcdifgrp {
+		fsl,pins = <
+			IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00			0x00000060
+			IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01			0x00000060
+			IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02			0x00000060
+			IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03		0x00000060
+			IMX8DXL_UART1_TX_ADMA_LCDIF_D04			0x00000060
+			IMX8DXL_UART1_RX_ADMA_LCDIF_D05			0x00000060
+			IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06		0x00000060
+			IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07		0x00000060
+			IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08			0x00000060
+			IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09			0x00000060
+			IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10			0x00000060
+			IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11			0x00000060
+			IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12			0x00000060
+			IMX8DXL_ADC_IN1_ADMA_LCDIF_D13			0xc600004c
+			IMX8DXL_ADC_IN0_ADMA_LCDIF_D14			0xc600004c
+			IMX8DXL_ADC_IN3_ADMA_LCDIF_D15			0xc600004c
+			IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC		0x00000060
+			IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET		0x00000060
+			IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN			0x00000060
+			IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC		0x00000060
+			IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK		0x00000060
+		>;
+	};
+};
+
+&adma_lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif>;
+	status = "okay";
+
+	assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>,
+			  <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>,
+			  <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>;
+	assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>,
+				 <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+	assigned-clock-rates = <0>, <24000000>, <711000000>;
+
+	port@0 {
+		lcdif_out: endpoint {
+			remote-endpoint = <&panel_in>;
+		};
+	};
+};