diff options
author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-02 17:13:48 +0800 |
---|---|---|
committer | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-09-09 02:45:38 +0800 |
commit | 65aa1b7ba2415762b15d77886624239c22bf6540 (patch) | |
tree | 3c3f98c7bc62492f82719f760d30a610ac2052d0 /arch/arm64 | |
parent | 70f26e7ba51640ae9379de986627e8fbe274c8dd (diff) |
MLK-24752-1 arch: arm64: imx8m: add IR support
Add IR support for i.MX8MM/MN/MQ.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'arch/arm64')
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 13 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 13 | ||||
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 13 |
3 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index bdf343f99e7e..f9616967d8f0 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -47,6 +47,13 @@ #reset-cells = <0>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -682,6 +689,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 6a576d74c538..8c736e0fe45c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -46,6 +46,13 @@ #reset-cells = <0>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -171,6 +178,12 @@ >; }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 1252fc08dcf8..e18b82d3afd5 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -41,6 +41,13 @@ #reset-cells = <0>; }; + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir_recv>; + }; + resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -813,6 +820,12 @@ }; + pinctrl_ir_recv: ir-recv { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f + >; + }; + pinctrl_csi1_pwn: csi1_pwn_grp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 |