diff options
author | Guoniu.zhou <guoniu.zhou@nxp.com> | 2019-10-25 09:17:00 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:08:45 +0800 |
commit | 908ef148d7c32174613b84d95fb52f47b8f0f0f0 (patch) | |
tree | 2ee009d7f0ec4d428b66a5edb828e1ec215b1ff2 /arch/arm64 | |
parent | 57101fca3cb286205b4f6d15be7d90c2364a31c5 (diff) |
arm64: dts: imx8mn: add device nodes support for camera
Camera subsystem of imx8mn is consist of ISI, MIPI CSI and OV5640
sensor, add device nodes for them.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 67 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 102 |
2 files changed, 169 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 6ff4ec67f9a5..c9a1bd4dff34 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -298,6 +298,19 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_csi_pwn: csi_pwn_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_csi_rst: csi_rst_grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; }; &i2c3 { @@ -345,6 +358,32 @@ AVDD-supply = <®_audio_board>; DVDD-supply = <®_audio_board>; }; + + ov5640_mipi_0: ov5640_mipi@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + csi_id = <0>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + status = "okay"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + data-lanes = <1 2>; + clocks-lanes = <0>; + }; + }; + }; }; &fec1 { @@ -570,3 +609,31 @@ "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; status = "okay"; }; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + port@0 { + reg = <0>; + mipi1_sensor_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + }; +}; + +&isi_0 { + status = "okay"; + + cap_device { + status = "okay"; + }; +}; + +&cameradev { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a56e95ed58b1..42cb2ac63088 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -38,6 +38,8 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + isi0 = &isi_0; + csi0 = &mipi_csi_1; }; cpus { @@ -1049,4 +1051,104 @@ #reset-cells = <1>; }; }; + + isi_resets: isi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + isi-soft-resetn { + compatible = "isi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_ISI_PROC_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_ISI_APB_CLK_RESET>; + }; + + isi-clk-enable { + compatible = "isi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_ISI_PROC_CLK_EN>, + <&dispmix_clk_en IMX8MN_ISI_APB_CLK_EN>; + }; + + }; + + mipi_csi_resets: mipi-csi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + csi-soft-resetn { + compatible = "csi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_CSI_PCLK_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_CSI_ACLK_RESET>; + }; + + csi-clk-enable { + compatible = "csi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_CSI_PCLK_EN>, + <&dispmix_clk_en IMX8MN_MIPI_CSI_ACLK_EN>; + }; + + csi-mipi-reset { + compatible = "csi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_S_RESET>; + }; + }; + + mipi2csi_gasket: gasket@32e28060 { + compatible = "syscon"; + reg = <0x0 0x32e28060 0x0 0x28>; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + isi_0: isi@0x32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x0 0x32e20000 0x0 0x2000>; + power-domains = <&dispmix_pd>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interface = <2 0 2>; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + resets = <&isi_resets>; + status = "disabled"; + + cap_device { + compatible = "imx-isi-capture"; + status = "disabled"; + }; + }; + + mipi_csi_1: csi@32e30000 { + compatible = "fsl,imx8mn-mipi-csi"; + reg = <0x0 0x32e30000 0x0 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>, <125000000>; + bus-width = <4>; + csi-gpr = <&mipi2csi_gasket>; + power-domains = <&mipi_pd>; + resets = <&mipi_csi_resets>; + status = "disabled"; + }; + }; }; |