diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-04-19 15:20:44 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:03:55 +0800 |
| commit | addcb262998f862c944e7b2b1f8d60159f5a720a (patch) | |
| tree | da46d565291ea5ef2167f0aefae124c216407f64 /arch/arm64 | |
| parent | 97717f1b49dacee12aeaeb57de7dd25c660ef481 (diff) | |
ARM64: dts: freescale: imx8qxp: add lpuart1 dma support
Add lpuart1 with dma support.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
[ Aisheng: change title as lpuart1 is already there ]
[ Aisheng: fix upgrade conflicts ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 15 |
2 files changed, 24 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 7ec961765fde..954be815b4ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -143,7 +143,15 @@ adma_subsys: bus@59000000 { clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_1>; + assigned-clocks = <&clk IMX_ADMA_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>; + power-domain-names = "uart", "rxdma", "txdma"; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 913fc835f8c5..15270646587f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -115,6 +115,12 @@ status = "okay"; }; +&adma_lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; @@ -356,6 +362,15 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + pinctrl_pcieb: pcieagrp{ fsl,pins = < IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 |