diff options
author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-13 11:14:38 +0800 |
---|---|---|
committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-03-24 11:24:49 +0800 |
commit | f3db6a0c22d60738307b6228cd893e07e81e11a5 (patch) | |
tree | a78b12a0143dde3c284d76aed36a1a0e4cf1cc82 /arch/arm64 | |
parent | dc62e993e136e31c9d3f97bbbb46727139b08f50 (diff) |
MLK-23666 arm64: dts: correct the legacy intx of imx8dxl pcie
Correct the legacy INTX numbers of the iMX8DXL PCIe.
Use the internal PLL as PCIe REF clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 4 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index ef488d151793..f479daf6552c 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -152,7 +152,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "clk_ext_sel"; - gpio = <&pca6416_1 10 GPIO_ACTIVE_LOW>; + gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>; regulator-always-on; }; @@ -506,7 +506,7 @@ pinctrl-0 = <&pinctrl_pcieb>; clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; - ext_osc = <1>; + ext_osc = <0>; epdev_on-supply = <&epdev_on>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index 43c67be8500f..859dcb246963 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -22,4 +22,11 @@ &pcieb { interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; }; |