diff options
| author | Robby Cai <R63905@freescale.com> | 2010-01-20 20:35:12 +0800 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-05-25 11:09:56 +0200 |
| commit | 460880faa9e2b08a336b35840664e2d7fdc019cb (patch) | |
| tree | bc574dd84f1337850d525199f62ae411700b44e8 /arch/arm | |
| parent | ebeb7921233812989c7c779921b98a7742bb99a0 (diff) | |
ENGR00117720-1 MX28: Add MSL codes to support MX28EVK
Add the MSL codes(New Framework) for MX28,
including clock, gpio, pinctrl, interrupt, timer, DMA, etc.
Signed-off-by: Fred Fan <r01011@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm')
51 files changed, 11238 insertions, 7 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e57008ccf3bf..29867ae7a1b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -313,6 +313,17 @@ config ARCH_STMP3XXX help Support for systems based on the Freescale 3xxx CPUs. +config ARCH_MXS + bool "Freescale i.MXS family soc" + select HAVE_CLK + select ARCH_REQUIRE_GPIOLIB + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select COMMON_CLKDEV + help + Support for Freescale i.MXS family of processors. + config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -718,6 +729,8 @@ source "arch/arm/mach-at91/Kconfig" source "arch/arm/plat-mxc/Kconfig" +source "arch/arm/plat-mxs/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-ns9xxx/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 726328e21e78..624af95ebcf3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -136,6 +136,7 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 +machine-$(CONFIG_ARCH_MX28) := mx28 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX35) := mx35 machine-$(CONFIG_ARCH_MX37) := mx37 @@ -172,6 +173,7 @@ plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c +plat-$(CONFIG_ARCH_MXS) := mxs plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig new file mode 100644 index 000000000000..435360116915 --- /dev/null +++ b/arch/arm/configs/imx28evk_defconfig @@ -0,0 +1,1059 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Mon Jan 25 15:59:49 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +# CONFIG_CLASSIC_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_DMA_ZONE_SIZE=16 + +# +# Freescale i.MXS implementations +# +CONFIG_ARCH_MX28=y +CONFIG_MACH_MX28EVK=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOUSE_GPIO is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_STACKTRACE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig new file mode 100644 index 000000000000..a46d7f02d450 --- /dev/null +++ b/arch/arm/mach-mx28/Kconfig @@ -0,0 +1,8 @@ +choice + prompt "Select i.MXS board type" + +config MACH_MX28EVK + bool "Freescale MX28 EVK board" + depends on ARCH_MX28 + +endchoice diff --git a/arch/arm/mach-mx28/Makefile b/arch/arm/mach-mx28/Makefile new file mode 100644 index 000000000000..530dd1132049 --- /dev/null +++ b/arch/arm/mach-mx28/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the linux kernel. +# +obj-y += pinctrl.o clock.o device.o + +# Board select +obj-$(CONFIG_MACH_MX28EVK) += mx28evk.o mx28evk_pins.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/arm/mach-mx28/Makefile.boot b/arch/arm/mach-mx28/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-mx28/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c new file mode 100644 index 000000000000..6c21cfb1ab9f --- /dev/null +++ b/arch/arm/mach-mx28/clock.c @@ -0,0 +1,877 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/clock.h> + +#include "regs-clkctrl.h" + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) + +/* external clock input */ +static struct clk xtal_clk[]; +static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; + +static unsigned long enet_mii_phy_rate; + +static int mx28_raw_enable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } + return 0; +} + +static void mx28_raw_disable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } +} + +static unsigned long xtal_get_rate(struct clk *clk) +{ + int id = clk - xtal_clk; + return xtal_clk_rate[id]; +} + +static struct clk xtal_clk[] = { + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, +}; + +static struct clk ref_xtal_clk = { + .parent = &xtal_clk[0], +}; + +static unsigned long pll_get_rate(struct clk *clk); +static int pll_enable(struct clk *clk); +static void pll_disable(struct clk *clk); +static struct clk pll_clk[] = { + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .enable = pll_enable, + .disable = pll_disable, + } +}; + +static unsigned long pll_get_rate(struct clk *clk) +{ + if (clk == (pll_clk + 2)) + return 50000000; + return 480000000; +} + +static int pll_enable(struct clk *clk) +{ + int timeout = 100; + unsigned long reg; + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER | + BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL0CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL0CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER | + BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL1CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL1CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + udelay(10); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return -ENODEV; +} + +static void pll_disable(struct clk *clk) +{ + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER | + BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_CLR); + return; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER | + BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_CLR); + return; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return; +} + +static inline unsigned long +ref_clk_get_rate(unsigned long base, unsigned int div) +{ + unsigned long rate = base / 1000; + return 1000 * ((rate * 18) / div); +} + +static unsigned long ref_cpu_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_CPUFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_cpu_clk = { + .parent = &pll_clk[0], + .get_rate = ref_cpu_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATECPU, +}; + +static unsigned long ref_emi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_EMIFRAC; + reg >>= BP_CLKCTRL_FRAC0_EMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_emi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_emi_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEEMI, +}; + +static unsigned long ref_io_get_rate(struct clk *clk); +static struct clk ref_io_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO0, + }, + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO1, + }, +}; + +static unsigned long ref_io_get_rate(struct clk *clk) +{ + unsigned int reg; + if (clk == ref_io_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO0FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO0FRAC; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO1FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO1FRAC; + } + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static unsigned long ref_pix_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_PIXFRAC; + reg >>= BP_CLKCTRL_FRAC1_PIXFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_pix_clk = { + .parent = &pll_clk[0], + .get_rate = ref_pix_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEPIX, +}; + +static unsigned long ref_hsadc_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_HSADCFRAC; + reg >>= BP_CLKCTRL_FRAC1_HSADCFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_hsadc_clk = { + .parent = &pll_clk[0], + .get_rate = ref_hsadc_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEHSADC, +}; + +static unsigned long ref_gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_GPMIFRAC; + reg >>= BP_CLKCTRL_FRAC1_GPMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_gpmi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_gpmi_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEGPMI, +}; + +static unsigned long cpu_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + if (clk->parent == &ref_cpu_clk) + reg = (reg & BM_CLKCTRL_CPU_DIV_CPU) >> BP_CLKCTRL_CPU_DIV_CPU; + else + reg = (reg & BM_CLKCTRL_CPU_DIV_XTAL) >> + BP_CLKCTRL_CPU_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk cpu_clk = { + .parent = &ref_cpu_clk, + .get_rate = cpu_get_rate, +}; + +static unsigned long uart_get_rate(struct clk *clk) +{ + unsigned int div; + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) & + BM_CLKCTRL_XTAL_DIV_UART; + return clk->parent->get_rate(clk->parent) / div; +} + +static struct clk uart_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE, + .get_rate = uart_get_rate, +}; + +static struct clk pwm_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE, +}; + +static unsigned long clk_32k_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static struct clk clk_32k = { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE, + .get_rate = clk_32k_get_rate, +}; + +static unsigned long lradc_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 16; +} + +static struct clk lradc_clk = { + .parent = &clk_32k, + .flags = RATE_FIXED, + .get_rate = lradc_get_rate, +}; + +static unsigned long x_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS) & + BM_CLKCTRL_XBUS_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk x_clk = { + .parent = &ref_xtal_clk, + .get_rate = x_get_rate, +}; + +static struct clk ana_clk = { + .parent = &ref_xtal_clk, +}; + +static unsigned long rtc_get_rate(struct clk *clk) +{ + if (clk->parent == &xtal_clk[2]) + return clk->parent->get_rate(clk->parent); + return clk->parent->get_rate(clk->parent) / 768; +} + +static struct clk rtc_clk = { + .parent = &ref_xtal_clk, + .get_rate = rtc_get_rate, +}; + +static struct clk flexcan_clk[] = { + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN0, + }, + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN1, + }, +}; + +static unsigned long h_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk h_clk = { + .parent = &cpu_clk, + .get_rate = h_get_rate, +}; + +static struct clk ocrom_clk = { + .parent = &h_clk, +}; + +static unsigned long emi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI); + if (clk->parent == &ref_emi_clk) + reg = (reg & BM_CLKCTRL_EMI_DIV_EMI); + else + reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk emi_clk = { + .parent = &ref_emi_clk, + .get_rate = emi_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .enable_bits = BM_CLKCTRL_EMI_CLKGATE, +}; + +static unsigned long ssp_get_rate(struct clk *clk); + +static struct clk ssp_clk[] = { + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .enable_bits = BM_CLKCTRL_SSP0_CLKGATE, + }, + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .enable_bits = BM_CLKCTRL_SSP1_CLKGATE, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .enable_bits = BM_CLKCTRL_SSP2_CLKGATE, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .enable_bits = BM_CLKCTRL_SSP3_CLKGATE, + }, +}; + +static unsigned long ssp_get_rate(struct clk *clk) +{ + unsigned int reg; + switch (clk - ssp_clk) { + case 0: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0) & + BM_CLKCTRL_SSP0_DIV; + break; + case 1: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1) & + BM_CLKCTRL_SSP1_DIV; + break; + case 2: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2) & + BM_CLKCTRL_SSP2_DIV; + break; + case 3: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3) & + BM_CLKCTRL_SSP3_DIV; + break; + default: + return 0; + } + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->get_rate(clk->parent); + long div; + + div = (__raw_readl(clk->scale_reg) >> clk->scale_bits) & + BM_CLKCTRL_DIS_LCDIF_DIV; + if (div) + rate /= div; + + return rate; +} + +static int lcdif_set_rate(struct clk *clk, unsigned long rate) +{ + int reg_val; + + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_DIS_LCDIF_DIV | BM_CLKCTRL_DIS_LCDIF_CLKGATE); + reg_val |= (1 << BP_CLKCTRL_DIS_LCDIF_DIV) & BM_CLKCTRL_DIS_LCDIF_DIV; + __raw_writel(reg_val, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + } + + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + reg_val |= BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF; + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + + return 0; +} + +static struct clk dis_lcdif_clk = { + .parent = &pll_clk[0], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .busy_bits = 29, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .enable_bits = 31, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 14, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, +}; + +static unsigned long hsadc_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + reg = (reg & BM_CLKCTRL_HSADC_FREQDIV) >> BP_CLKCTRL_HSADC_FREQDIV; + return clk->parent->get_rate(clk->parent) / ((1 << reg) * 9); +} + +static int hsadc_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg = clk->parent->get_rate(clk->parent); + if ((reg / rate) % 9) + return -EINVAL; + reg = reg / 9; + switch (reg) { + case 1: + reg = BM_CLKCTRL_HSADC_RESETB; + break; + case 2: + reg = 1 | BM_CLKCTRL_HSADC_RESETB; + break; + case 4: + reg = 2 | BM_CLKCTRL_HSADC_RESETB; + break; + case 8: + reg = 3 | BM_CLKCTRL_HSADC_RESETB; + break; + default: + return -EINVAL; + } + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + return 0; +} + +static unsigned long hsadc_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg = clk->parent->get_rate(clk->parent); + div = ((reg / rate) + 8) / 9; + if (div <= 1) + return reg; + if (div > 4) + return reg >> 3; + if (div > 2) + return reg >> 2; + return reg >> 1; +} + +static struct clk hsadc_clk = { + .parent = &ref_hsadc_clk, + .get_rate = hsadc_get_rate, + .set_rate = hsadc_set_rate, + .round_rate = hsadc_round_rate, +}; + +static unsigned long gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & + BM_CLKCTRL_GPMI_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk gpmi_clk = { + .parent = &ref_gpmi_clk, + .get_rate = gpmi_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .enable_bits = BM_CLKCTRL_GPMI_CLKGATE, +}; + +static unsigned long saif_get_rate(struct clk *clk); +static struct clk saif_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .enable_bits = BM_CLKCTRL_SAIF0_CLKGATE, + }, + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .enable_bits = BM_CLKCTRL_SAIF1_CLKGATE, + }, +}; + +static unsigned long saif_get_rate(struct clk *clk) +{ + unsigned long reg; + if (clk == saif_clk) + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0) & + BM_CLKCTRL_SAIF0_DIV; + else + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1) & + BM_CLKCTRL_SAIF1_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long pcmspdif_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 4; +} + +static struct clk pcmspdif_clk = { + .parent = &pll_clk[0], + .get_rate = pcmspdif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF, + .enable_bits = BM_CLKCTRL_SPDIF_CLKGATE, +}; + +static struct clk_lookup onchip_clocks[] = { + { + .con_id = "xtal.0", + .clk = &xtal_clk[0], + }, + { + .con_id = "xtal.1", + .clk = &xtal_clk[1], + }, + { + .con_id = "xtal.2", + .clk = &xtal_clk[2], + }, + { + .con_id = "pll.0", + .clk = &pll_clk[0], + }, + { + .con_id = "pll.1", + .clk = &pll_clk[1], + }, + { + .con_id = "pll.2", + .clk = &pll_clk[2], + }, + { + .con_id = "ref_xtal", + .clk = &ref_xtal_clk, + }, + { + .con_id = "ref_cpu", + .clk = &ref_cpu_clk, + }, + { + .con_id = "ref_emi", + .clk = &ref_emi_clk, + }, + { + .con_id = "ref_io.0", + .clk = &ref_io_clk[0], + }, + { + .con_id = "ref_io.1", + .clk = &ref_io_clk[1], + }, + { + .con_id = "ref_pix", + .clk = &ref_pix_clk, + }, + { + .con_id = "ref_hsadc", + .clk = &ref_hsadc_clk, + }, + { + .con_id = "ref_gpmi", + .clk = &ref_gpmi_clk, + }, + { + .con_id = "ana", + .clk = &ana_clk, + }, + { + .con_id = "rtc", + .clk = &rtc_clk, + }, + { + .con_id = "cpu", + .clk = &cpu_clk, + }, + { + .con_id = "h", + .clk = &h_clk, + }, + { + .con_id = "x", + .clk = &x_clk, + }, + { + .con_id = "ocrom", + .clk = &ocrom_clk, + }, + { + .con_id = "clk_32k", + .clk = &clk_32k, + }, + { + .con_id = "uart", + .clk = &uart_clk, + }, + { + .con_id = "pwm", + .clk = &pwm_clk, + }, + { + .con_id = "lradc", + .clk = &lradc_clk, + }, + { + .con_id = "ssp.0", + .clk = &ssp_clk[0], + }, + { + .con_id = "ssp.1", + .clk = &ssp_clk[1], + }, + { + .con_id = "ssp.2", + .clk = &ssp_clk[2], + }, + { + .con_id = "ssp.3", + .clk = &ssp_clk[3], + }, + { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, + { + .con_id = "spdif", + .clk = &pcmspdif_clk, + }, + { + .con_id = "saif.0", + .clk = &saif_clk[0], + }, + { + .con_id = "saif.1", + .clk = &saif_clk[1], + }, + { + .con_id = "emi", + .clk = &emi_clk, + }, + { + .con_id = "dis_lcdif", + .clk = &dis_lcdif_clk, + }, + { + .con_id = "hsadc", + .clk = &hsadc_clk, + }, + { + .con_id = "flexcan.0", + .clk = &flexcan_clk[0], + }, + { + .con_id = "flexcan.1", + .clk = &flexcan_clk[1], + }, +}; + +static void mx28_clock_scan(void) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) + cpu_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) + dis_lcdif_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + emi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) + ssp_clk[3].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) + ssp_clk[2].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) + ssp_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) + ssp_clk[0].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) + gpmi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) + saif_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) + saif_clk[0].parent = &ref_xtal_clk; +}; + +void __init mx28_set_input_clk(unsigned long xtal0, + unsigned long xtal1, + unsigned long xtal2, unsigned long enet) +{ + xtal_clk_rate[0] = xtal0; + xtal_clk_rate[1] = xtal1; + xtal_clk_rate[2] = xtal2; + enet_mii_phy_rate = enet; +} + +void __init mx28_clock_init(void) +{ + int i; + mx28_clock_scan(); + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) + clk_register(&onchip_clocks[i]); + + clk_enable(&cpu_clk); + clk_enable(&emi_clk); +} diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c new file mode 100644 index 000000000000..133370ef5491 --- /dev/null +++ b/arch/arm/mach-mx28/device.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/regs-timrot.h> +#include <mach/device.h> +#include <mach/dma.h> + +#include "device.h" + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct resource duart_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DUART_PHYS_ADDR, + .end = DUART_PHYS_ADDR + 0x1000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_DUART, + .end = IRQ_DUART, + }, +}; + +static void __init mx28_init_duart(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-duart", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = duart_resource; + pdev->num_resources = ARRAY_SIZE(duart_resource); + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_duart(void) +{ +} +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct resource mxs_ahb_apbh_res = { + .flags = IORESOURCE_MEM, + .start = APBH_DMA_PHYS_ADDR, + .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = 16, +}; + +static struct resource mxs_ahb_apbx_res = { + .flags = IORESOURCE_MEM, + .start = APBX_DMA_PHYS_ADDR, + .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbx_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBX, + .chan_num = 16, +}; + +static void __init mx28_init_dma(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + lookup = mxs_get_devices("mxs-dma"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + if (!strcmp(pdev->name, "mxs-dma-apbh")) { + pdev->resource = &mxs_ahb_apbh_res; + pdev->dev.platform_data = &mxs_ahb_apbh_data; + } else if (!strcmp(pdev->name, "mxs-dma-apbx")) { + pdev->resource = &mxs_ahb_apbx_res; + pdev->dev.platform_data = &mxs_ahb_apbx_data; + } else + continue; + pdev->num_resources = 1; + mxs_add_device(pdev, 0); + } +} +#else +static void mx28_init_dma(void) +{ + ; +} +#endif + +int __init mx28_device_init(void) +{ + mx28_init_dma(); + mx28_init_duart(); + + return 0; +} + +static struct __initdata map_desc mx28_io_desc[] = { + { + .virtual = MX28_SOC_IO_VIRT_BASE, + .pfn = __phys_to_pfn(MX28_SOC_IO_PHYS_BASE), + .length = MX28_SOC_IO_AREA_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} + +void __init mx28_irq_init(void) +{ + avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS); +} + +static void mx28_timer_init(void) +{ + int i, reg; + mx28_clock_init(); + + mx28_timer.clk = clk_get(NULL, "clk_32k"); + if (mx28_timer.clk == NULL || IS_ERR(mx28_timer.clk)) + return; + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + for (i = 0; i < 10000; i++) { + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + if (!(reg & BM_TIMROT_ROTCTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return; + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + for (i = 0; i < 4; i++) { + if (!(reg & (BM_TIMROT_ROTCTRL_TIM0_PRESENT << i))) + continue; + mx28_timer.id = i; + mx28_timer.irq = IRQ_TIMER0 + i; + mxs_timer_init(&mx28_timer); + return; + } +} + +struct mxs_sys_timer mx28_timer = { + .timer = { + .init = mx28_timer_init, + }, + .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL, + .base = IO_ADDRESS(TIMROT_PHYS_ADDR), +}; diff --git a/arch/arm/mach-mx28/device.h b/arch/arm/mach-mx28/device.h new file mode 100644 index 000000000000..6fac8f670c58 --- /dev/null +++ b/arch/arm/mach-mx28/device.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DEVICE_H__ +#define __ASM_ARCH_MACH_DEVICE_H__ + +extern struct mxs_sys_timer mx28_timer; + +extern void __init mx28_map_io(void); +extern void __init mx28_clock_init(void); +extern void __init mx28_irq_init(void); +extern int __init mx28_pinctrl_init(void); +extern int __init mx28_gpio_init(void); +extern int __init mx28_device_init(void); +extern void __init mx28_init_auart(void); +extern void __init +mx28_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long); + +#endif diff --git a/arch/arm/mach-mx28/gpio.c b/arch/arm/mach-mx28/gpio.c new file mode 100644 index 000000000000..d936df89326b --- /dev/null +++ b/arch/arm/mach-mx28/gpio.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (input) + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET); + + return 0; +} + +static int mx28_gpio_get(struct mxs_gpio_port *port, int pin) +{ + unsigned int data; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + data = __raw_readl(base + HW_PINCTRL_DIN0); + return data & (1 << pin); +} + +static void mx28_gpio_set(struct mxs_gpio_port *port, int pin, int data) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (data) + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR); +} + +static unsigned int mx28_gpio_irq_stat(struct mxs_gpio_port *port) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + return mask; +} + +static int +mx28_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type) +{ + unsigned int level, pol; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level = 0; + pol = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + level = 0; + pol = 0; + break; + case IRQ_TYPE_LEVEL_HIGH: + level = 1; + pol = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + level = 1; + pol = 0; + break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + + if (level) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR); + + if (pol) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR); + + return 0; +} + +static void mx28_gpio_unmask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET); +} + +static void mx28_gpio_mask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR); +} + +static void mx28_gpio_ack_irq(struct mxs_gpio_port *port, int pin) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = 1 << pin; + mask &= __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + if (mask) + __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR); +} + +static struct mxs_gpio_port mx28_gpios[] = { + { + .irq = IRQ_GPIO0, + }, + { + .irq = IRQ_GPIO1, + }, + { + .irq = IRQ_GPIO2, + }, + { + .irq = IRQ_GPIO3, + }, + { + .irq = IRQ_GPIO4, + }, +}; + +static struct mxs_gpio_chip mx28_gpio_chip = { + .set_dir = mx28_gpio_direction, + .get = mx28_gpio_get, + .set = mx28_gpio_set, + .get_irq_stat = mx28_gpio_irq_stat, + .set_irq_type = mx28_gpio_set_irq_type, + .unmask_irq = mx28_gpio_unmask_irq, + .mask_irq = mx28_gpio_mask_irq, + .ack_irq = mx28_gpio_ack_irq, +}; + +int __init mx28_gpio_init(void) +{ + int i; + unsigned int reg; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL); + for (i = 0; i < ARRAY_SIZE(mx28_gpios); i++) { + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i; + if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i))) + continue; + mxs_set_gpio_chip(&mx28_gpios[i], &mx28_gpio_chip); + mx28_gpios[i].id = i; + __raw_writel(0, base + HW_PINCTRL_IRQEN0); + __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0); + mx28_gpios[i].child_irq = MXS_GPIO_IRQ_START + + (i * PINS_PER_BANK); + mxs_add_gpio_port(&mx28_gpios[i]); + } + return 0; +} diff --git a/arch/arm/mach-mx28/include/mach/dma.h b/arch/arm/mach-mx28/include/mach/dma.h new file mode 100644 index 000000000000..ad8076c5d8f3 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_UART4_RX = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_03, + MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_I2C0, + MXS_DMA_CHANNEL_AHB_APBX_I2C1, + MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h new file mode 100644 index 000000000000..1680f06a7f16 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/mx28.h @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX28_H__ +#define __ASM_ARCH_MACH_MX28_H__ + +#include <asm/sizes.h> + +#define MX28_SOC_IO_PHYS_BASE 0x80000000 +#define MX28_SOC_IO_VIRT_BASE 0xF0000000 +#define MX28_SOC_IO_AREA_SIZE SZ_1M + +#define ICOLL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x000000) +#define HSADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x002000) +#define APBH_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x004000) +#define PERFMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x006000) +#define BCH_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x010000) +#define SSP1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x012000) +#define SSP2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x014000) +#define SSP3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x016000) +#define PINCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x022000) +#define APBX_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x030000) +#define CAN0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x032000) +#define CAN1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x034000) +#define SIMDBG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C000) +#define SIMGPMISEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C200) +#define SIMSSPSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C300) +#define SIMMEMSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C400) +#define GPIOMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C500) +#define SIMENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C700) +#define ARMJTAG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C800) +#define CLKCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x046000) +#define LRADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x056000) +#define I2C0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x058000) +#define I2C1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x05A000) +#define PWM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x068000) +#define AUART0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06A000) +#define AUART1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06E000) +#define AUART3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x070000) +#define AUART4_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x072000) +#define DUART_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x074000) +#define USBPHY0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07C000) +#define USBPHY1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07E000) +#define USBCTRL0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x080000) +#define USBCTRL1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x090000) +#define DFLPT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0C0000) +#define DRAM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0E0000) +#define ENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0F0000) + +/* IRQ Definitions */ +#define IRQ_BATT_BRNOUT 0 +#define IRQ_VDD_BRNOUT 1 +#define IRQ_VDDIO_BRNOUT 2 +#define IRQ_VDDA_BRNOUT 3 +#define IRQ_VDD5V_DROOP 4 +#define IRQ_DCDC4P2_BRNOUT 5 +#define IRQ_VDD5V 6 +#define IRQ_RESV7 7 +#define IRQ_CAN0 8 +#define IRQ_CAN1 9 +#define IRQ_LRADC_TOUCH 10 +#define IRQ_RESV11 11 +#define IRQ_RESV12 12 +#define IRQ_HSADC 13 +#define IRQ_IRADC_THRESH0 14 +#define IRQ_IRADC_THRESH1 15 +#define IRQ_LRADC_CH0 16 +#define IRQ_LRADC_CH1 17 +#define IRQ_LRADC_CH2 18 +#define IRQ_LRADC_CH3 19 +#define IRQ_LRADC_CH4 20 +#define IRQ_LRADC_CH5 21 +#define IRQ_LRADC_CH6 22 +#define IRQ_LRADC_CH7 23 +#define IRQ_LRADC_BUTTON0 24 +#define IRQ_LRADC_BUTTON1 25 +#define IRQ_RESV26 26 +#define IRQ_PERFMON 27 +#define IRQ_RTC_1MSEC 28 +#define IRQ_RTC_ALARM 29 +#define IRQ_RESV30 30 +#define IRQ_COMMS 31 +#define IRQ_EMI_ERR 32 +#define IRQ_RESV33 33 +#define IRQ_RESV34 34 +#define IRQ_RESV35 35 +#define IRQ_RESV36 36 +#define IRQ_RESV37 37 +#define IRQ_LCDIF 38 +#define IRQ_PXP 39 +#define IRQ_RESV40 40 +#define IRQ_BCH 41 +#define IRQ_GPMI 42 +#define IRQ_RESV43 43 +#define IRQ_RESV44 44 +#define IRQ_SPDIF_ERROR 45 +#define IRQ_RESV46 46 +#define IRQ_DUART 47 +#define IRQ_TIMER0 48 +#define IRQ_TIMER1 49 +#define IRQ_TIMER2 50 +#define IRQ_TIMER3 51 +#define IRQ_DCP_VMI 52 +#define IRQ_DCP 53 +#define IRQ_DCP_SECURE 54 +#define IRQ_RESV55 55 +#define IRQ_RESV56 56 +#define IRQ_RESV57 57 +#define IRQ_SAIF1 58 +#define IRQ_SAIF0 59 +#define IRQ_RESV60 60 +#define IRQ_RESV61 61 +#define IRQ_RESV62 62 +#define IRQ_RESV63 63 +#define IRQ_RESV64 64 +#define IRQ_RESV65 65 +#define IRQ_SPDIF_DMA 66 +#define IRQ_RESV67 67 +#define IRQ_I2C0_DMA 68 +#define IRQ_I2C1_DMA 69 +#define IRQ_AUART0_RX_DMA 70 +#define IRQ_AUART0_TX_DMA 71 +#define IRQ_AUART1_RX_DMA 72 +#define IRQ_AUART1_TX_DMA 73 +#define IRQ_AUART2_RX_DMA 74 +#define IRQ_AUART2_TX_DMA 75 +#define IRQ_AUART3_RX_DMA 76 +#define IRQ_AUART3_TX_DMA 77 +#define IRQ_AUART4_RX_DMA 78 +#define IRQ_AUART4_TX_DMA 79 +#define IRQ_SAIF0_DMA 80 +#define IRQ_SAIF1_DMA 81 +#define IRQ_SSP0_DMA 82 +#define IRQ_SSP1_DMA 83 +#define IRQ_SSP2_DMA 84 +#define IRQ_SSP3_DMA 85 +#define IRQ_LCDIF_DMA 86 +#define IRQ_HSADC_DMA 87 +#define IRQ_GPMI_DMA 88 +#define IRQ_DIGCTL_DEBUG_TRAP 89 +#define IRQ_RESV90 90 +#define IRQ_RESV91 91 +#define IRQ_USB1 92 +#define IRQ_USB0 93 +#define IRQ_USB1_WAKEUP 94 +#define IRQ_USB0_WAKEUP 95 +#define IRQ_SSP0 96 +#define IRQ_SSP1 97 +#define IRQ_SSP2 98 +#define IRQ_SSP3 99 +#define IRQ_ENET_SWI 100 +#define IRQ_ENET_MAC0 101 +#define IRQ_ENET_MAC1 102 +#define IRQ_ENET_MAC0_1588 103 +#define IRQ_ENET_MAC1_1588 104 +#define IRQ_RESV105 105 +#define IRQ_RESV106 106 +#define IRQ_RESV107 107 +#define IRQ_RESV108 108 +#define IRQ_RESV109 109 +#define IRQ_I2C1_ERROR 110 +#define IRQ_I2C0_ERROR 111 +#define IRQ_AUART0 112 +#define IRQ_AUART1 113 +#define IRQ_AUART2 114 +#define IRQ_AUART3 115 +#define IRQ_AUART4 116 +#define IRQ_RESV117 117 +#define IRQ_RESV118 118 +#define IRQ_RESV119 119 +#define IRQ_RESV120 120 +#define IRQ_RESV121 121 +#define IRQ_RESV122 122 +#define IRQ_GPIO4 123 +#define IRQ_GPIO3 124 +#define IRQ_GPIO2 125 +#define IRQ_GPIO1 126 +#define IRQ_GPIO0 127 + +#define ARCH_NR_IRQS 128 + +#define MX28_SOC_IO_ADDRESS(x) \ + ((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE) + +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \ + MX28_SOC_IO_AREA_SIZE) ? \ + MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF) + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/regs-timrot.h b/arch/arm/mach-mx28/include/mach/regs-timrot.h new file mode 100644 index 000000000000..125b835e19ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-timrot.h @@ -0,0 +1,293 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.40 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40) +#define BP_TIMROT_TIMCTRLn_RSRVD3 16 +#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD2 12 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF + +/* + * multi-register-define name HW_TIMROT_RUNNING_COUNTn + * base 0x00000030 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40) +#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_FIXED_COUNTn + * base 0x00000040 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40) +#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_MATCH_COUNTn + * base 0x00000050 + * count 4 + * offset 0x40 + */ +#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40) +#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0 +#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF +#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v) + +#define HW_TIMROT_TIMCTRL3 (0x000000e0) +#define HW_TIMROT_TIMCTRL3_SET (0x000000e4) +#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8) +#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 12 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF + +#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0) + +#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v) + +#define HW_TIMROT_FIXED_COUNT3 (0x00000100) + +#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v) + +#define HW_TIMROT_VERSION (0x00000120) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx28/mx28_pins.h b/arch/arm/mach-mx28/mx28_pins.h new file mode 100644 index 000000000000..a87ab9d6fc81 --- /dev/null +++ b/arch/arm/mach-mx28/mx28_pins.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +#include <mach/pinctrl.h> + +/* + * Define MX28 pins, the pin name corresponds to MX28 hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0) +#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1) +#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2) +#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3) +#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4) +#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5) +#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6) +#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7) +#define PINID_GPMI_CE0N MXS_PIN_ENCODE(0, 16) +#define PINID_GPMI_CE1N MXS_PIN_ENCODE(0, 17) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_CE3N MXS_PIN_ENCODE(0, 19) +#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 20) +#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 21) +#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 22) +#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 23) +#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 24) +#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 25) +#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 26) +#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 27) +#define PINID_GPMI_RESETN MXS_PIN_ENCODE(0, 28) + +/* Bank 1 */ +#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0) +#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1) +#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2) +#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3) +#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4) +#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5) +#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6) +#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7) +#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8) +#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9) +#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10) +#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11) +#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12) +#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13) +#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14) +#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15) +#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16) +#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17) +#define PINID_LCD_D18 MXS_PIN_ENCODE(1, 18) +#define PINID_LCD_D19 MXS_PIN_ENCODE(1, 19) +#define PINID_LCD_D20 MXS_PIN_ENCODE(1, 20) +#define PINID_LCD_D21 MXS_PIN_ENCODE(1, 21) +#define PINID_LCD_D22 MXS_PIN_ENCODE(1, 22) +#define PINID_LCD_D23 MXS_PIN_ENCODE(1, 23) +#define PINID_LCD_RD_E MXS_PIN_ENCODE(1, 24) +#define PINID_LCD_WR_RWN MXS_PIN_ENCODE(1, 25) +#define PINID_LCD_RS MXS_PIN_ENCODE(1, 26) +#define PINID_LCD_CS MXS_PIN_ENCODE(1, 27) +#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 28) +#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 29) +#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 30) +#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 31) + +/* Bank 2 */ +#define PINID_SSP0_DATA0 MXS_PIN_ENCODE(2, 0) +#define PINID_SSP0_DATA1 MXS_PIN_ENCODE(2, 1) +#define PINID_SSP0_DATA2 MXS_PIN_ENCODE(2, 2) +#define PINID_SSP0_DATA3 MXS_PIN_ENCODE(2, 3) +#define PINID_SSP0_DATA4 MXS_PIN_ENCODE(2, 4) +#define PINID_SSP0_DATA5 MXS_PIN_ENCODE(2, 5) +#define PINID_SSP0_DATA6 MXS_PIN_ENCODE(2, 6) +#define PINID_SSP0_DATA7 MXS_PIN_ENCODE(2, 7) +#define PINID_SSP0_CMD MXS_PIN_ENCODE(2, 8) +#define PINID_SSP0_DETECT MXS_PIN_ENCODE(2, 9) +#define PINID_SSP0_SCK MXS_PIN_ENCODE(2, 10) +#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 12) +#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 13) +#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 14) +#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 15) +#define PINID_SSP2_SCK MXS_PIN_ENCODE(2, 16) +#define PINID_SSP2_MOSI MXS_PIN_ENCODE(2, 17) +#define PINID_SSP2_MISO MXS_PIN_ENCODE(2, 18) +#define PINID_SSP2_SS0 MXS_PIN_ENCODE(2, 19) +#define PINID_SSP2_SS1 MXS_PIN_ENCODE(2, 20) +#define PINID_SSP2_SS2 MXS_PIN_ENCODE(2, 21) +#define PINID_SSP3_SCK MXS_PIN_ENCODE(2, 24) +#define PINID_SSP3_MOSI MXS_PIN_ENCODE(2, 25) +#define PINID_SSP3_MISO MXS_PIN_ENCODE(2, 26) +#define PINID_SSP3_SS0 MXS_PIN_ENCODE(2, 27) + +/* Bank 3 */ +#define PINID_AUART0_RX MXS_PIN_ENCODE(3, 0) +#define PINID_AUART0_TX MXS_PIN_ENCODE(3, 1) +#define PINID_AUART0_CTS MXS_PIN_ENCODE(3, 2) +#define PINID_AUART0_RTS MXS_PIN_ENCODE(3, 3) +#define PINID_AUART1_RX MXS_PIN_ENCODE(3, 4) +#define PINID_AUART1_TX MXS_PIN_ENCODE(3, 5) +#define PINID_AUART1_CTS MXS_PIN_ENCODE(3, 6) +#define PINID_AUART1_RTS MXS_PIN_ENCODE(3, 7) +#define PINID_AUART2_RX MXS_PIN_ENCODE(3, 8) +#define PINID_AUART2_TX MXS_PIN_ENCODE(3, 9) +#define PINID_AUART2_CTS MXS_PIN_ENCODE(3, 10) +#define PINID_AUART2_RTS MXS_PIN_ENCODE(3, 11) +#define PINID_AUART3_RX MXS_PIN_ENCODE(3, 12) +#define PINID_AUART3_TX MXS_PIN_ENCODE(3, 13) +#define PINID_AUART3_CTS MXS_PIN_ENCODE(3, 14) +#define PINID_AUART3_RTS MXS_PIN_ENCODE(3, 15) +#define PINID_PWM0 MXS_PIN_ENCODE(3, 16) +#define PINID_PWM1 MXS_PIN_ENCODE(3, 17) +#define PINID_PWM2 MXS_PIN_ENCODE(3, 18) +#define PINID_SAIF0_MCLK MXS_PIN_ENCODE(3, 20) +#define PINID_SAIF0_LRCLK MXS_PIN_ENCODE(3, 21) +#define PINID_SAIF0_BITCLK MXS_PIN_ENCODE(3, 22) +#define PINID_SAIF0_SDATA0 MXS_PIN_ENCODE(3, 23) +#define PINID_I2C0_SCL MXS_PIN_ENCODE(3, 24) +#define PINID_I2C0_SDA MXS_PIN_ENCODE(3, 25) +#define PINID_SAIF1_SDATA0 MXS_PIN_ENCODE(3, 26) +#define PINID_SPDIF MXS_PIN_ENCODE(3, 27) +#define PINID_PWM3 MXS_PIN_ENCODE(3, 28) +#define PINID_PWM4 MXS_PIN_ENCODE(3, 29) +#define PINID_LCD_RESET MXS_PIN_ENCODE(3, 30) + +/* Bank 4 */ +#define PINID_ENET0_MDC MXS_PIN_ENCODE(4, 0) +#define PINID_ENET0_MDIO MXS_PIN_ENCODE(4, 1) +#define PINID_ENET0_RX_EN MXS_PIN_ENCODE(4, 2) +#define PINID_ENET0_RXD0 MXS_PIN_ENCODE(4, 3) +#define PINID_ENET0_RXD1 MXS_PIN_ENCODE(4, 4) +#define PINID_ENET0_TX_CLK MXS_PIN_ENCODE(4, 5) +#define PINID_ENET0_TX_EN MXS_PIN_ENCODE(4, 6) +#define PINID_ENET0_TXD0 MXS_PIN_ENCODE(4, 7) +#define PINID_ENET0_TXD1 MXS_PIN_ENCODE(4, 8) +#define PINID_ENET0_RXD2 MXS_PIN_ENCODE(4, 9) +#define PINID_ENET0_RXD3 MXS_PIN_ENCODE(4, 10) +#define PINID_ENET0_TXD2 MXS_PIN_ENCODE(4, 11) +#define PINID_ENET0_TXD3 MXS_PIN_ENCODE(4, 12) +#define PINID_ENET0_RX_CLK MXS_PIN_ENCODE(4, 13) +#define PINID_ENET0_COL MXS_PIN_ENCODE(4, 14) +#define PINID_ENET0_CRS MXS_PIN_ENCODE(4, 15) +#define PINID_ENET_CLK MXS_PIN_ENCODE(4, 16) +#define PINID_JTAG_RTCK MXS_PIN_ENCODE(4, 20) +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c new file mode 100644 index 000000000000..cf7eaaa23457 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/pinctrl.h> + +#include "device.h" +#include "mx28evk.h" + +static void __init fixup_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mx28_set_input_clk(24000000, 24000000, 32000, 50000000); +} + +static void __init mx28evk_device_init(void) +{ + /* Add mx28evk special code */ +} + +static void __init mx28evk_init_machine(void) +{ + mx28_pinctrl_init(); + mx28_gpio_init(); + mx28evk_pins_init(); + mx28_device_init(); + mx28evk_device_init(); +} + +MACHINE_START(MX28EVK, "Freescale MX28EVK board") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .fixup = fixup_board, + .map_io = mx28_map_io, + .init_irq = mx28_irq_init, + .init_machine = mx28evk_init_machine, + .timer = &mx28_timer.timer, +MACHINE_END diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h new file mode 100644 index 000000000000..c141749cc183 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_MACH_MX28EVK_H +#define __ASM_ARM_MACH_MX28EVK_H + +extern void __init mx28evk_pins_init(void); +#endif /* __ASM_ARM_MACH_MX28EVK_H */ diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c new file mode 100644 index 000000000000..58d6ba6c3eb7 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk_pins.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/gpio.h> + +#include <mach/pinctrl.h> + +#include "mx28_pins.h" + +static struct pin_desc mx28evk_fixed_pins[] = { + { + .name = "DUART.RX", + .id = PINID_PWM0, + .fun = PIN_FUN3, + }, + { + .name = "DUART.TX", + .id = PINID_PWM1, + .fun = PIN_FUN3, + }, +}; + +void __init mx28evk_pins_init(void) +{ + int i; + struct pin_desc *pin; + for (i = 0; i < ARRAY_SIZE(mx28evk_fixed_pins); i++) { + pin = &mx28evk_fixed_pins[i]; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->input) + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + else + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + } + } +} diff --git a/arch/arm/mach-mx28/pinctrl.c b/arch/arm/mach-mx28/pinctrl.c new file mode 100644 index 000000000000..32c6e1f6177f --- /dev/null +++ b/arch/arm/mach-mx28/pinctrl.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id) +{ + int bank; + bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK); + if (bank == MXS_PIN_BANK_MAX) + return -EINVAL; + *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK); + return bank; +} + +static unsigned int mx28_get_gpio(struct pin_bank *bank, unsigned int id) +{ + if (bank->gpio_port >= MXS_NON_GPIO) + return -EINVAL; + return bank->gpio_port * PINS_PER_BANK + id; +} + +static void mx28_set_strength(struct pin_bank *bank, + unsigned int id, enum pad_strength strength) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id *= 4; + __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER); + __raw_writel(strength << id, addr + SET_REGISTER); +} + +static void mx28_set_voltage(struct pin_bank *bank, + unsigned int id, enum pad_voltage volt) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id = id * 4 + 2; + if (volt == PAD_1_8V) + __raw_writel(1 << id, addr + CLR_REGISTER); + else + __raw_writel(1 << id, addr + SET_REGISTER); +} + +static void mx28_set_pullup(struct pin_bank *bank, unsigned int id, int pullup) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0; + addr += 0x10 * bank->id; + if (pullup) + __raw_writel(1 << id, addr + SET_REGISTER); + else + __raw_writel(1 << id, addr + CLR_REGISTER); +} + +static void mx28_set_type(struct pin_bank *bank, + unsigned int id, enum pin_fun cfg) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + __raw_writel(0x3 << id, addr + CLR_REGISTER); + __raw_writel(cfg << id, addr + SET_REGISTER); +} + +static struct pin_bank mx28_pin_banks[6] = { + [0] = { + .id = 0, + .gpio_port = 0, + }, + [1] = { + .id = 1, + .gpio_port = 1, + }, + [2] = { + .id = 2, + .gpio_port = 2, + }, + [3] = { + .id = 3, + .gpio_port = 3, + }, + [4] = { + .id = 4, + .gpio_port = 4, + }, + [5] = { + .id = 5, + .gpio_port = MXS_NON_GPIO, + } +}; + +static struct pinctrl_chip mx28_pinctrl = { + .name = "pinctrl", + .banks = mx28_pin_banks, + .pin2id = mx28_pin2id, + .get_gpio = mx28_get_gpio, + .set_strength = mx28_set_strength, + .set_voltage = mx28_set_voltage, + .set_pullup = mx28_set_pullup, + .set_type = mx28_set_type, +}; + +int __init mx28_pinctrl_init(void) +{ + int i; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + mx28_pinctrl.bank_size = ARRAY_SIZE(mx28_pin_banks); + return mxs_set_pinctrl_chip(&mx28_pinctrl); +} diff --git a/arch/arm/mach-mx28/regs-clkctrl.h b/arch/arm/mach-mx28/regs-clkctrl.h new file mode 100644 index 000000000000..161860c2fcf0 --- /dev/null +++ b/arch/arm/mach-mx28/regs-clkctrl.h @@ -0,0 +1,634 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + +#define HW_CLKCTRL_PLL0CTRL0 (0x00000000) +#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) +#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) + +#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL1CTRL0 (0x00000020) +#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) +#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) +#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) + +#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 +#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) + +#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL2CTRL0 (0x00000040) +#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) +#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) +#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) + +#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 +#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) +#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 +#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 +#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) +#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 +#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF +#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) + +#define HW_CLKCTRL_CPU (0x00000050) +#define HW_CLKCTRL_CPU_SET (0x00000054) +#define HW_CLKCTRL_CPU_CLR (0x00000058) +#define HW_CLKCTRL_CPU_TOG (0x0000005c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000060) +#define HW_CLKCTRL_HBUS_SET (0x00000064) +#define HW_CLKCTRL_HBUS_CLR (0x00000068) +#define HW_CLKCTRL_HBUS_TOG (0x0000006c) + +#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 +#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 +#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000070) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 12 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000080) +#define HW_CLKCTRL_XTAL_SET (0x00000084) +#define HW_CLKCTRL_XTAL_CLR (0x00000088) +#define HW_CLKCTRL_XTAL_TOG (0x0000008c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BP_CLKCTRL_XTAL_RSRVD2 27 +#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 +#define BF_CLKCTRL_XTAL_RSRVD2(v) \ + (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_SSP0 (0x00000090) + +#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP0_BUSY 0x20000000 +#define BP_CLKCTRL_SSP0_RSRVD1 10 +#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP0_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) +#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP0_DIV 0 +#define BM_CLKCTRL_SSP0_DIV 0x000001FF +#define BF_CLKCTRL_SSP0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP0_DIV) + +#define HW_CLKCTRL_SSP1 (0x000000a0) + +#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP1_BUSY 0x20000000 +#define BP_CLKCTRL_SSP1_RSRVD1 10 +#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP1_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) +#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP1_DIV 0 +#define BM_CLKCTRL_SSP1_DIV 0x000001FF +#define BF_CLKCTRL_SSP1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP1_DIV) + +#define HW_CLKCTRL_SSP2 (0x000000b0) + +#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP2_BUSY 0x20000000 +#define BP_CLKCTRL_SSP2_RSRVD1 10 +#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP2_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) +#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP2_DIV 0 +#define BM_CLKCTRL_SSP2_DIV 0x000001FF +#define BF_CLKCTRL_SSP2_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP2_DIV) + +#define HW_CLKCTRL_SSP3 (0x000000c0) + +#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP3_BUSY 0x20000000 +#define BP_CLKCTRL_SSP3_RSRVD1 10 +#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP3_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) +#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP3_DIV 0 +#define BM_CLKCTRL_SSP3_DIV 0x000001FF +#define BF_CLKCTRL_SSP3_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP3_DIV) + +#define HW_CLKCTRL_GPMI (0x000000d0) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x000000e0) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000f0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_SAIF0 (0x00000100) + +#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF0_RSRVD1 17 +#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) +#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF0_DIV 0 +#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) + +#define HW_CLKCTRL_SAIF1 (0x00000110) + +#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF1_RSRVD1 17 +#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) +#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF1_DIV 0 +#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) + +#define HW_CLKCTRL_DIS_LCDIF (0x00000120) + +#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 +#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 +#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ + (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) +#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 +#define BP_CLKCTRL_DIS_LCDIF_DIV 0 +#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF +#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) + +#define HW_CLKCTRL_ETM (0x00000130) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 8 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000007F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_ENET (0x00000140) + +#define BM_CLKCTRL_ENET_SLEEP 0x80000000 +#define BM_CLKCTRL_ENET_DISABLE 0x40000000 +#define BM_CLKCTRL_ENET_STATUS 0x20000000 +#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 +#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 +#define BP_CLKCTRL_ENET_DIV_TIME 21 +#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 +#define BF_CLKCTRL_ENET_DIV_TIME(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) +#define BP_CLKCTRL_ENET_TIME_SEL 19 +#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 +#define BF_CLKCTRL_ENET_TIME_SEL(v) \ + (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) +#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 +#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 +#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 +#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 +#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 +#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 +#define BP_CLKCTRL_ENET_RSRVD0 0 +#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF +#define BF_CLKCTRL_ENET_RSRVD0(v) \ + (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) + +#define HW_CLKCTRL_HSADC (0x00000150) + +#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 +#define BM_CLKCTRL_HSADC_RESETB 0x40000000 +#define BP_CLKCTRL_HSADC_FREQDIV 28 +#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 +#define BF_CLKCTRL_HSADC_FREQDIV(v) \ + (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) +#define BP_CLKCTRL_HSADC_RSRVD1 0 +#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF +#define BF_CLKCTRL_HSADC_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) + +#define HW_CLKCTRL_FLEXCAN (0x00000160) + +#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 +#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 +#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 +#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 +#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF +#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) + +#define HW_CLKCTRL_FRAC0 (0x000001b0) +#define HW_CLKCTRL_FRAC0_SET (0x000001b4) +#define HW_CLKCTRL_FRAC0_CLR (0x000001b8) +#define HW_CLKCTRL_FRAC0_TOG (0x000001bc) + +#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 +#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC0_IO0FRAC 24 +#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 +#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 +#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC0_IO1FRAC 16 +#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 +#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC0_EMIFRAC 8 +#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) +#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC0_CPUFRAC 0 +#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x000001c0) +#define HW_CLKCTRL_FRAC1_SET (0x000001c4) +#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) +#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) + +#define BP_CLKCTRL_FRAC1_RSRVD2 24 +#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 +#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) +#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 +#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC1_GPMIFRAC 16 +#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 +#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC1_HSADCFRAC 8 +#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 +#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC1_PIXFRAC 0 +#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F +#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) + +#define HW_CLKCTRL_CLKSEQ (0x000001d0) +#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) +#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) +#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) + +#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ + (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 +#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 +#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 +#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 + +#define HW_CLKCTRL_RESET (0x000001e0) + +#define BP_CLKCTRL_RESET_RSRVD 6 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 +#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 +#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 +#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x000001f0) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000200) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-mx28/regs-pinctrl.h b/arch/arm/mach-mx28/regs-pinctrl.h new file mode 100644 index 000000000000..03c7f15da080 --- /dev/null +++ b/arch/arm/mach-mx28/regs-pinctrl.h @@ -0,0 +1,2673 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 25 +#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT4 0x01000000 +#define BM_PINCTRL_CTRL_PRESENT3 0x00800000 +#define BM_PINCTRL_CTRL_PRESENT2 0x00400000 +#define BM_PINCTRL_CTRL_PRESENT1 0x00200000 +#define BM_PINCTRL_CTRL_PRESENT0 0x00100000 +#define BP_PINCTRL_CTRL_RSRVD1 5 +#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010 +#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008 +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) + +#define BP_PINCTRL_MUXSEL0_RSRVD0 16 +#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000 +#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) + +#define BP_PINCTRL_MUXSEL1_RSRVD0 26 +#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000 +#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) + +#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_RSRVD0 22 +#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000 +#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) + +#define BP_PINCTRL_MUXSEL5_RSRVD1 24 +#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000 +#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_RSRVD0 12 +#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000 +#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) + +#define BP_PINCTRL_MUXSEL7_RSRVD1 30 +#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000 +#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_RSRVD0 6 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_MUXSEL8 (0x00000180) +#define HW_PINCTRL_MUXSEL8_SET (0x00000184) +#define HW_PINCTRL_MUXSEL8_CLR (0x00000188) +#define HW_PINCTRL_MUXSEL8_TOG (0x0000018c) + +#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00) + +#define HW_PINCTRL_MUXSEL9 (0x00000190) +#define HW_PINCTRL_MUXSEL9_SET (0x00000194) +#define HW_PINCTRL_MUXSEL9_CLR (0x00000198) +#define HW_PINCTRL_MUXSEL9_TOG (0x0000019c) + +#define BP_PINCTRL_MUXSEL9_RSRVD1 10 +#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00 +#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20) +#define BP_PINCTRL_MUXSEL9_RSRVD0 2 +#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC +#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16) + +#define HW_PINCTRL_MUXSEL10 (0x000001a0) +#define HW_PINCTRL_MUXSEL10_SET (0x000001a4) +#define HW_PINCTRL_MUXSEL10_CLR (0x000001a8) +#define HW_PINCTRL_MUXSEL10_TOG (0x000001ac) + +#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00) + +#define HW_PINCTRL_MUXSEL11 (0x000001b0) +#define HW_PINCTRL_MUXSEL11_SET (0x000001b4) +#define HW_PINCTRL_MUXSEL11_CLR (0x000001b8) +#define HW_PINCTRL_MUXSEL11_TOG (0x000001bc) + +#define BP_PINCTRL_MUXSEL11_RSRVD1 22 +#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000 +#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26) +#define BP_PINCTRL_MUXSEL11_RSRVD0 16 +#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000 +#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16) + +#define HW_PINCTRL_MUXSEL12 (0x000001c0) +#define HW_PINCTRL_MUXSEL12_SET (0x000001c4) +#define HW_PINCTRL_MUXSEL12_CLR (0x000001c8) +#define HW_PINCTRL_MUXSEL12_TOG (0x000001cc) + +#define BP_PINCTRL_MUXSEL12_RSRVD0 30 +#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00) + +#define HW_PINCTRL_MUXSEL13 (0x000001d0) +#define HW_PINCTRL_MUXSEL13_SET (0x000001d4) +#define HW_PINCTRL_MUXSEL13_CLR (0x000001d8) +#define HW_PINCTRL_MUXSEL13_TOG (0x000001dc) + +#define BP_PINCTRL_MUXSEL13_RSRVD0 18 +#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000300) +#define HW_PINCTRL_DRIVE0_SET (0x00000304) +#define HW_PINCTRL_DRIVE0_CLR (0x00000308) +#define HW_PINCTRL_DRIVE0_TOG (0x0000030c) + +#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000310) +#define HW_PINCTRL_DRIVE1_SET (0x00000314) +#define HW_PINCTRL_DRIVE1_CLR (0x00000318) +#define HW_PINCTRL_DRIVE1_TOG (0x0000031c) + +#define BP_PINCTRL_DRIVE1_RSRVD0 0 +#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v) + +#define HW_PINCTRL_DRIVE2 (0x00000320) +#define HW_PINCTRL_DRIVE2_SET (0x00000324) +#define HW_PINCTRL_DRIVE2_CLR (0x00000328) +#define HW_PINCTRL_DRIVE2_TOG (0x0000032c) + +#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000330) +#define HW_PINCTRL_DRIVE3_SET (0x00000334) +#define HW_PINCTRL_DRIVE3_CLR (0x00000338) +#define HW_PINCTRL_DRIVE3_TOG (0x0000033c) + +#define BP_PINCTRL_DRIVE3_RSRVD5 20 +#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000340) +#define HW_PINCTRL_DRIVE4_SET (0x00000344) +#define HW_PINCTRL_DRIVE4_CLR (0x00000348) +#define HW_PINCTRL_DRIVE4_TOG (0x0000034c) + +#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000350) +#define HW_PINCTRL_DRIVE5_SET (0x00000354) +#define HW_PINCTRL_DRIVE5_CLR (0x00000358) +#define HW_PINCTRL_DRIVE5_TOG (0x0000035c) + +#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000360) +#define HW_PINCTRL_DRIVE6_SET (0x00000364) +#define HW_PINCTRL_DRIVE6_CLR (0x00000368) +#define HW_PINCTRL_DRIVE6_TOG (0x0000036c) + +#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000370) +#define HW_PINCTRL_DRIVE7_SET (0x00000374) +#define HW_PINCTRL_DRIVE7_CLR (0x00000378) +#define HW_PINCTRL_DRIVE7_TOG (0x0000037c) + +#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA) +#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000380) +#define HW_PINCTRL_DRIVE8_SET (0x00000384) +#define HW_PINCTRL_DRIVE8_CLR (0x00000388) +#define HW_PINCTRL_DRIVE8_TOG (0x0000038c) + +#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000390) +#define HW_PINCTRL_DRIVE9_SET (0x00000394) +#define HW_PINCTRL_DRIVE9_CLR (0x00000398) +#define HW_PINCTRL_DRIVE9_TOG (0x0000039c) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BP_PINCTRL_DRIVE9_RSRVD3 12 +#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE9_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000003a0) +#define HW_PINCTRL_DRIVE10_SET (0x000003a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000003a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000003ac) + +#define BP_PINCTRL_DRIVE10_RSRVD6 24 +#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE10_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000003b0) +#define HW_PINCTRL_DRIVE11_SET (0x000003b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000003b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000003bc) + +#define BP_PINCTRL_DRIVE11_RSRVD4 16 +#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000003c0) +#define HW_PINCTRL_DRIVE12_SET (0x000003c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000003c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000003cc) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000003d0) +#define HW_PINCTRL_DRIVE13_SET (0x000003d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000003d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000003dc) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000003e0) +#define HW_PINCTRL_DRIVE14_SET (0x000003e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000003e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000003ec) + +#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA) +#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BP_PINCTRL_DRIVE14_RSRVD3 12 +#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE14_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_DRIVE15 (0x000003f0) +#define HW_PINCTRL_DRIVE15_SET (0x000003f4) +#define HW_PINCTRL_DRIVE15_CLR (0x000003f8) +#define HW_PINCTRL_DRIVE15_TOG (0x000003fc) + +#define BP_PINCTRL_DRIVE15_RSRVD7 28 +#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE15_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7) +#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA) +#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA) +#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA) +#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA) +#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA) +#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA) +#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA) + +#define HW_PINCTRL_DRIVE16 (0x00000400) +#define HW_PINCTRL_DRIVE16_SET (0x00000404) +#define HW_PINCTRL_DRIVE16_CLR (0x00000408) +#define HW_PINCTRL_DRIVE16_TOG (0x0000040c) + +#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA) +#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA) +#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA) +#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA) +#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA) +#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA) +#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA) +#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA) + +#define HW_PINCTRL_DRIVE17 (0x00000410) +#define HW_PINCTRL_DRIVE17_SET (0x00000414) +#define HW_PINCTRL_DRIVE17_CLR (0x00000418) +#define HW_PINCTRL_DRIVE17_TOG (0x0000041c) + +#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA) +#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA) +#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA) +#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA) +#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA) +#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA) +#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA) +#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA) + +#define HW_PINCTRL_DRIVE18 (0x00000420) +#define HW_PINCTRL_DRIVE18_SET (0x00000424) +#define HW_PINCTRL_DRIVE18_CLR (0x00000428) +#define HW_PINCTRL_DRIVE18_TOG (0x0000042c) + +#define BP_PINCTRL_DRIVE18_RSRVD3 20 +#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000 +#define BF_PINCTRL_DRIVE18_RSRVD3(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3) +#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA) +#define BP_PINCTRL_DRIVE18_RSRVD1 4 +#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0 +#define BF_PINCTRL_DRIVE18_RSRVD1(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1) +#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA) + +#define HW_PINCTRL_DRIVE19 (0x00000430) +#define HW_PINCTRL_DRIVE19_SET (0x00000434) +#define HW_PINCTRL_DRIVE19_CLR (0x00000438) +#define HW_PINCTRL_DRIVE19_TOG (0x0000043c) + +#define BP_PINCTRL_DRIVE19_RSRVD0 0 +#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v) + +#define HW_PINCTRL_PULL0 (0x00000600) +#define HW_PINCTRL_PULL0_SET (0x00000604) +#define HW_PINCTRL_PULL0_CLR (0x00000608) +#define HW_PINCTRL_PULL0_TOG (0x0000060c) + +#define BP_PINCTRL_PULL0_RSRVD1 29 +#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000 +#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000 +#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000 +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000 +#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000 +#define BP_PINCTRL_PULL0_RSRVD0 8 +#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000610) +#define HW_PINCTRL_PULL1_SET (0x00000614) +#define HW_PINCTRL_PULL1_CLR (0x00000618) +#define HW_PINCTRL_PULL1_TOG (0x0000061c) + +#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000 +#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000 +#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000 +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 +#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000 +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000 +#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000 +#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000 +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000 +#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000 +#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000 +#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000 +#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000 +#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000 +#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800 +#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400 +#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200 +#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100 +#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080 +#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040 +#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020 +#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010 +#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008 +#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004 +#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002 +#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001 + +#define HW_PINCTRL_PULL2 (0x00000620) +#define HW_PINCTRL_PULL2_SET (0x00000624) +#define HW_PINCTRL_PULL2_CLR (0x00000628) +#define HW_PINCTRL_PULL2_TOG (0x0000062c) + +#define BP_PINCTRL_PULL2_RSRVD2 28 +#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000 +#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000 +#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000 +#define BP_PINCTRL_PULL2_RSRVD1 22 +#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000 +#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000 +#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000 +#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000 +#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000 +#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000 +#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000 +#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000 +#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000 +#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000 +#define BM_PINCTRL_PULL2_RSRVD0 0x00000800 +#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400 +#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200 +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080 +#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040 +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000630) +#define HW_PINCTRL_PULL3_SET (0x00000634) +#define HW_PINCTRL_PULL3_CLR (0x00000638) +#define HW_PINCTRL_PULL3_TOG (0x0000063c) + +#define BM_PINCTRL_PULL3_RSRVD1 0x80000000 +#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000 +#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000 +#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000 +#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000 +#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000 +#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000 +#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000 +#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000 +#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000 +#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000 +#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000 +#define BM_PINCTRL_PULL3_RSRVD0 0x00080000 +#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000 +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_PULL4 (0x00000640) +#define HW_PINCTRL_PULL4_SET (0x00000644) +#define HW_PINCTRL_PULL4_CLR (0x00000648) +#define HW_PINCTRL_PULL4_TOG (0x0000064c) + +#define BP_PINCTRL_PULL4_RSRVD1 21 +#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PULL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1) +#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000 +#define BP_PINCTRL_PULL4_RSRVD0 17 +#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000 +#define BF_PINCTRL_PULL4_RSRVD0(v) \ + (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0) +#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000 +#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000 +#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000 +#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000 +#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000 +#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800 +#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400 +#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200 +#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100 +#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080 +#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040 +#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020 +#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010 +#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008 +#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004 +#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002 +#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001 + +#define HW_PINCTRL_PULL5 (0x00000650) +#define HW_PINCTRL_PULL5_SET (0x00000654) +#define HW_PINCTRL_PULL5_CLR (0x00000658) +#define HW_PINCTRL_PULL5_TOG (0x0000065c) + +#define BP_PINCTRL_PULL5_RSRVD1 27 +#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000 +#define BF_PINCTRL_PULL5_RSRVD1(v) \ + (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1) +#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000 +#define BP_PINCTRL_PULL5_RSRVD0 24 +#define BM_PINCTRL_PULL5_RSRVD0 0x03000000 +#define BF_PINCTRL_PULL5_RSRVD0(v) \ + (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0) +#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000 +#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000 +#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000 +#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000 +#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000 +#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000 +#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000 +#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000 +#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000 +#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000 +#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000 +#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000 +#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800 +#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400 +#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200 +#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100 +#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080 +#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040 +#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020 +#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010 +#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008 +#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004 +#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002 +#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001 + +#define HW_PINCTRL_PULL6 (0x00000660) +#define HW_PINCTRL_PULL6_SET (0x00000664) +#define HW_PINCTRL_PULL6_CLR (0x00000668) +#define HW_PINCTRL_PULL6_TOG (0x0000066c) + +#define BP_PINCTRL_PULL6_RSRVD1 25 +#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000 +#define BF_PINCTRL_PULL6_RSRVD1(v) \ + (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1) +#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000 +#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000 +#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000 +#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000 +#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000 +#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000 +#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000 +#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000 +#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000 +#define BM_PINCTRL_PULL6_RSRVD0 0x00008000 +#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000 +#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000 +#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000 +#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800 +#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400 +#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200 +#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100 +#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080 +#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040 +#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020 +#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010 +#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008 +#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004 +#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002 +#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000700) +#define HW_PINCTRL_DOUT0_SET (0x00000704) +#define HW_PINCTRL_DOUT0_CLR (0x00000708) +#define HW_PINCTRL_DOUT0_TOG (0x0000070c) + +#define BP_PINCTRL_DOUT0_RSRVD1 29 +#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOUT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1) +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT0_DOUT) + +#define HW_PINCTRL_DOUT1 (0x00000710) +#define HW_PINCTRL_DOUT1_SET (0x00000714) +#define HW_PINCTRL_DOUT1_CLR (0x00000718) +#define HW_PINCTRL_DOUT1_TOG (0x0000071c) + +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) (v) + +#define HW_PINCTRL_DOUT2 (0x00000720) +#define HW_PINCTRL_DOUT2_SET (0x00000724) +#define HW_PINCTRL_DOUT2_CLR (0x00000728) +#define HW_PINCTRL_DOUT2_TOG (0x0000072c) + +#define BP_PINCTRL_DOUT2_RSRVD1 28 +#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOUT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1) +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT2_DOUT) + +#define HW_PINCTRL_DOUT3 (0x00000730) +#define HW_PINCTRL_DOUT3_SET (0x00000734) +#define HW_PINCTRL_DOUT3_CLR (0x00000738) +#define HW_PINCTRL_DOUT3_TOG (0x0000073c) + +#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT3_DOUT 0 +#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT3_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT3_DOUT) + +#define HW_PINCTRL_DOUT4 (0x00000740) +#define HW_PINCTRL_DOUT4_SET (0x00000744) +#define HW_PINCTRL_DOUT4_CLR (0x00000748) +#define HW_PINCTRL_DOUT4_TOG (0x0000074c) + +#define BP_PINCTRL_DOUT4_RSRVD1 21 +#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOUT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1) +#define BP_PINCTRL_DOUT4_DOUT 0 +#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF +#define BF_PINCTRL_DOUT4_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT4_DOUT) + +#define HW_PINCTRL_DIN0 (0x00000900) +#define HW_PINCTRL_DIN0_SET (0x00000904) +#define HW_PINCTRL_DIN0_CLR (0x00000908) +#define HW_PINCTRL_DIN0_TOG (0x0000090c) + +#define BP_PINCTRL_DIN0_RSRVD1 29 +#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DIN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1) +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN0_DIN) + +#define HW_PINCTRL_DIN1 (0x00000910) +#define HW_PINCTRL_DIN1_SET (0x00000914) +#define HW_PINCTRL_DIN1_CLR (0x00000918) +#define HW_PINCTRL_DIN1_TOG (0x0000091c) + +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) (v) + +#define HW_PINCTRL_DIN2 (0x00000920) +#define HW_PINCTRL_DIN2_SET (0x00000924) +#define HW_PINCTRL_DIN2_CLR (0x00000928) +#define HW_PINCTRL_DIN2_TOG (0x0000092c) + +#define BP_PINCTRL_DIN2_RSRVD1 28 +#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DIN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1) +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN2_DIN) + +#define HW_PINCTRL_DIN3 (0x00000930) +#define HW_PINCTRL_DIN3_SET (0x00000934) +#define HW_PINCTRL_DIN3_CLR (0x00000938) +#define HW_PINCTRL_DIN3_TOG (0x0000093c) + +#define BM_PINCTRL_DIN3_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN3_DIN 0 +#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN3_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN3_DIN) + +#define HW_PINCTRL_DIN4 (0x00000940) +#define HW_PINCTRL_DIN4_SET (0x00000944) +#define HW_PINCTRL_DIN4_CLR (0x00000948) +#define HW_PINCTRL_DIN4_TOG (0x0000094c) + +#define BP_PINCTRL_DIN4_RSRVD1 21 +#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DIN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1) +#define BP_PINCTRL_DIN4_DIN 0 +#define BM_PINCTRL_DIN4_DIN 0x001FFFFF +#define BF_PINCTRL_DIN4_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN4_DIN) + +#define HW_PINCTRL_DOE0 (0x00000b00) +#define HW_PINCTRL_DOE0_SET (0x00000b04) +#define HW_PINCTRL_DOE0_CLR (0x00000b08) +#define HW_PINCTRL_DOE0_TOG (0x00000b0c) + +#define BP_PINCTRL_DOE0_RSRVD1 29 +#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOE0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1) +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE0_DOE) + +#define HW_PINCTRL_DOE1 (0x00000b10) +#define HW_PINCTRL_DOE1_SET (0x00000b14) +#define HW_PINCTRL_DOE1_CLR (0x00000b18) +#define HW_PINCTRL_DOE1_TOG (0x00000b1c) + +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) (v) + +#define HW_PINCTRL_DOE2 (0x00000b20) +#define HW_PINCTRL_DOE2_SET (0x00000b24) +#define HW_PINCTRL_DOE2_CLR (0x00000b28) +#define HW_PINCTRL_DOE2_TOG (0x00000b2c) + +#define BP_PINCTRL_DOE2_RSRVD1 28 +#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOE2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1) +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE2_DOE) + +#define HW_PINCTRL_DOE3 (0x00000b30) +#define HW_PINCTRL_DOE3_SET (0x00000b34) +#define HW_PINCTRL_DOE3_CLR (0x00000b38) +#define HW_PINCTRL_DOE3_TOG (0x00000b3c) + +#define BM_PINCTRL_DOE3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE3_DOE 0 +#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE3_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE3_DOE) + +#define HW_PINCTRL_DOE4 (0x00000b40) +#define HW_PINCTRL_DOE4_SET (0x00000b44) +#define HW_PINCTRL_DOE4_CLR (0x00000b48) +#define HW_PINCTRL_DOE4_TOG (0x00000b4c) + +#define BP_PINCTRL_DOE4_RSRVD1 21 +#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOE4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1) +#define BP_PINCTRL_DOE4_DOE 0 +#define BM_PINCTRL_DOE4_DOE 0x001FFFFF +#define BF_PINCTRL_DOE4_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE4_DOE) + +#define HW_PINCTRL_PIN2IRQ0 (0x00001000) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00001004) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00001008) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000100c) + +#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29 +#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1) +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ1 (0x00001010) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00001014) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00001018) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000101c) + +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ2 (0x00001020) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00001024) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00001028) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000102c) + +#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28 +#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000 +#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1) +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ3 (0x00001030) +#define HW_PINCTRL_PIN2IRQ3_SET (0x00001034) +#define HW_PINCTRL_PIN2IRQ3_CLR (0x00001038) +#define HW_PINCTRL_PIN2IRQ3_TOG (0x0000103c) + +#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ4 (0x00001040) +#define HW_PINCTRL_PIN2IRQ4_SET (0x00001044) +#define HW_PINCTRL_PIN2IRQ4_CLR (0x00001048) +#define HW_PINCTRL_PIN2IRQ4_TOG (0x0000104c) + +#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21 +#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1) +#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF +#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ) + +#define HW_PINCTRL_IRQEN0 (0x00001100) +#define HW_PINCTRL_IRQEN0_SET (0x00001104) +#define HW_PINCTRL_IRQEN0_CLR (0x00001108) +#define HW_PINCTRL_IRQEN0_TOG (0x0000110c) + +#define BP_PINCTRL_IRQEN0_RSRVD1 29 +#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQEN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1) +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN) + +#define HW_PINCTRL_IRQEN1 (0x00001110) +#define HW_PINCTRL_IRQEN1_SET (0x00001114) +#define HW_PINCTRL_IRQEN1_CLR (0x00001118) +#define HW_PINCTRL_IRQEN1_TOG (0x0000111c) + +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN2 (0x00001120) +#define HW_PINCTRL_IRQEN2_SET (0x00001124) +#define HW_PINCTRL_IRQEN2_CLR (0x00001128) +#define HW_PINCTRL_IRQEN2_TOG (0x0000112c) + +#define BP_PINCTRL_IRQEN2_RSRVD1 28 +#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQEN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1) +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN) + +#define HW_PINCTRL_IRQEN3 (0x00001130) +#define HW_PINCTRL_IRQEN3_SET (0x00001134) +#define HW_PINCTRL_IRQEN3_CLR (0x00001138) +#define HW_PINCTRL_IRQEN3_TOG (0x0000113c) + +#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN3_IRQEN 0 +#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN3_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN) + +#define HW_PINCTRL_IRQEN4 (0x00001140) +#define HW_PINCTRL_IRQEN4_SET (0x00001144) +#define HW_PINCTRL_IRQEN4_CLR (0x00001148) +#define HW_PINCTRL_IRQEN4_TOG (0x0000114c) + +#define BP_PINCTRL_IRQEN4_RSRVD1 21 +#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQEN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1) +#define BP_PINCTRL_IRQEN4_IRQEN 0 +#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF +#define BF_PINCTRL_IRQEN4_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN) + +#define HW_PINCTRL_IRQLEVEL0 (0x00001200) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00001204) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00001208) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x0000120c) + +#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29 +#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1) +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL1 (0x00001210) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00001214) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00001218) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x0000121c) + +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL2 (0x00001220) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00001224) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00001228) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x0000122c) + +#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28 +#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1) +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL3 (0x00001230) +#define HW_PINCTRL_IRQLEVEL3_SET (0x00001234) +#define HW_PINCTRL_IRQLEVEL3_CLR (0x00001238) +#define HW_PINCTRL_IRQLEVEL3_TOG (0x0000123c) + +#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL4 (0x00001240) +#define HW_PINCTRL_IRQLEVEL4_SET (0x00001244) +#define HW_PINCTRL_IRQLEVEL4_CLR (0x00001248) +#define HW_PINCTRL_IRQLEVEL4_TOG (0x0000124c) + +#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21 +#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1) +#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF +#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL) + +#define HW_PINCTRL_IRQPOL0 (0x00001300) +#define HW_PINCTRL_IRQPOL0_SET (0x00001304) +#define HW_PINCTRL_IRQPOL0_CLR (0x00001308) +#define HW_PINCTRL_IRQPOL0_TOG (0x0000130c) + +#define BP_PINCTRL_IRQPOL0_RSRVD1 29 +#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1) +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL) + +#define HW_PINCTRL_IRQPOL1 (0x00001310) +#define HW_PINCTRL_IRQPOL1_SET (0x00001314) +#define HW_PINCTRL_IRQPOL1_CLR (0x00001318) +#define HW_PINCTRL_IRQPOL1_TOG (0x0000131c) + +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL2 (0x00001320) +#define HW_PINCTRL_IRQPOL2_SET (0x00001324) +#define HW_PINCTRL_IRQPOL2_CLR (0x00001328) +#define HW_PINCTRL_IRQPOL2_TOG (0x0000132c) + +#define BP_PINCTRL_IRQPOL2_RSRVD1 28 +#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1) +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL) + +#define HW_PINCTRL_IRQPOL3 (0x00001330) +#define HW_PINCTRL_IRQPOL3_SET (0x00001334) +#define HW_PINCTRL_IRQPOL3_CLR (0x00001338) +#define HW_PINCTRL_IRQPOL3_TOG (0x0000133c) + +#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL3_IRQPOL 0 +#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL) + +#define HW_PINCTRL_IRQPOL4 (0x00001340) +#define HW_PINCTRL_IRQPOL4_SET (0x00001344) +#define HW_PINCTRL_IRQPOL4_CLR (0x00001348) +#define HW_PINCTRL_IRQPOL4_TOG (0x0000134c) + +#define BP_PINCTRL_IRQPOL4_RSRVD1 21 +#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1) +#define BP_PINCTRL_IRQPOL4_IRQPOL 0 +#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF +#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL) + +#define HW_PINCTRL_IRQSTAT0 (0x00001400) +#define HW_PINCTRL_IRQSTAT0_SET (0x00001404) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00001408) +#define HW_PINCTRL_IRQSTAT0_TOG (0x0000140c) + +#define BP_PINCTRL_IRQSTAT0_RSRVD1 29 +#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1) +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT1 (0x00001410) +#define HW_PINCTRL_IRQSTAT1_SET (0x00001414) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00001418) +#define HW_PINCTRL_IRQSTAT1_TOG (0x0000141c) + +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT2 (0x00001420) +#define HW_PINCTRL_IRQSTAT2_SET (0x00001424) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00001428) +#define HW_PINCTRL_IRQSTAT2_TOG (0x0000142c) + +#define BP_PINCTRL_IRQSTAT2_RSRVD1 28 +#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1) +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT3 (0x00001430) +#define HW_PINCTRL_IRQSTAT3_SET (0x00001434) +#define HW_PINCTRL_IRQSTAT3_CLR (0x00001438) +#define HW_PINCTRL_IRQSTAT3_TOG (0x0000143c) + +#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT4 (0x00001440) +#define HW_PINCTRL_IRQSTAT4_SET (0x00001444) +#define HW_PINCTRL_IRQSTAT4_CLR (0x00001448) +#define HW_PINCTRL_IRQSTAT4_TOG (0x0000144c) + +#define BP_PINCTRL_IRQSTAT4_RSRVD1 21 +#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1) +#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF +#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT) + +#define HW_PINCTRL_EMI_ODT_CTRL (0x00001a40) +#define HW_PINCTRL_EMI_ODT_CTRL_SET (0x00001a44) +#define HW_PINCTRL_EMI_ODT_CTRL_CLR (0x00001a48) +#define HW_PINCTRL_EMI_ODT_CTRL_TOG (0x00001a4c) + +#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28 +#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000 +#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \ + (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \ + (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \ + (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \ + (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \ + (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \ + (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \ + (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \ + (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \ + (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \ + (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \ + (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \ + (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \ + (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \ + (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD) + +#define HW_PINCTRL_EMI_DS_CTRL (0x00001b80) +#define HW_PINCTRL_EMI_DS_CTRL_SET (0x00001b84) +#define HW_PINCTRL_EMI_DS_CTRL_CLR (0x00001b88) +#define HW_PINCTRL_EMI_DS_CTRL_TOG (0x00001b8c) + +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \ + (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16 +#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000 +#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \ + (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11 +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0) +#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12 +#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000 +#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \ + (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA) +#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10 +#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00 +#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \ + (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA) +#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8 +#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300 +#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \ + (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \ + (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \ + (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C +#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \ + (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \ + (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/plat-mxs/Kconfig b/arch/arm/plat-mxs/Kconfig new file mode 100644 index 000000000000..304de21d41cc --- /dev/null +++ b/arch/arm/plat-mxs/Kconfig @@ -0,0 +1,47 @@ +if ARCH_MXS + +menu "Freescale i.MXS implementations" + +choice + prompt "Select i.MXS chip family" + +config ARCH_MX28 + bool "Freescale MX28" + select CPU_ARM926T + select ZONE_DMA + select MXS_ICOLL + select MXS_DMA_ENGINE + ---help--- + Support Freescale MX28 chips + +endchoice + +if ARCH_MX28 +source arch/arm/mach-mx28/Kconfig +endif + +config DMA_ZONE_SIZE + int "DMA memory zone size" + range 0 32 + default 16 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers +endmenu + +config MXS_ICOLL + bool + +config MXS_EARLY_CONSOLE + bool "Enable console early" + default y + help + Enable console early for kernel debug. + +config MXS_DMA_ENGINE + bool "Enable DMA ENGINE support" + default y + help + Support DMA controller on AHB-APBH and AHB-APBX Bridge + +endif diff --git a/arch/arm/plat-mxs/Makefile b/arch/arm/plat-mxs/Makefile new file mode 100644 index 000000000000..aa7a2c5cf167 --- /dev/null +++ b/arch/arm/plat-mxs/Makefile @@ -0,0 +1,16 @@ +# +# Makefile for the linux kernel. +# +# Object file lists. +obj-y += core.o clock.o pinctrl.o device.o timer.o + +obj-$(CONFIG_GENERIC_GPIO) += gpio.o + +obj-$(CONFIG_MXS_ICOLL) += icoll.o + +obj-$(CONFIG_MXS_DMA_ENGINE) += dmaengine.o dma-apbh.o dma-apbx.o + +# Power Management + +# charging/current limitation testing + diff --git a/arch/arm/plat-mxs/clock.c b/arch/arm/plat-mxs/clock.c new file mode 100644 index 000000000000..a4bd61cb699e --- /dev/null +++ b/arch/arm/plat-mxs/clock.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/spinlock.h> + +#include <mach/clock.h> + +static DEFINE_SPINLOCK(clockfw_lock); + +/* + *------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *------------------------------------------------------------------------- + */ +int __clk_get(struct clk *clk) +{ + if (clk->ref < CLK_REF_LIMIT) + clk->ref += CLK_REF_UNIT; + return clk->ref < CLK_REF_LIMIT; +} + +void __clk_put(struct clk *clk) +{ + if (clk->ref & CLK_REF_LIMIT) + clk->ref -= CLK_REF_UNIT; +} + +static void default_clk_disable(struct clk *clk) +{ + if (clk->enable_reg) + __raw_writel(clk->enable_bits, clk->enable_reg + SET_REGISTER); +} + +static int default_clk_enable(struct clk *clk) +{ + if (clk->enable_reg) + __raw_writel(clk->enable_bits, clk->enable_reg + CLR_REGISTER); + return 0; +} + +static unsigned long default_get_rate(struct clk *clk) +{ + if (clk->parent && clk->parent->get_rate) + return clk->parent->get_rate(clk->parent); + return 0L; +} + +static void __clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->ref) + return; + + if ((--clk->ref) & CLK_EN_MASK) + return; + + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->secondary); + __clk_disable(clk->parent); +} + +static int __clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if ((clk->ref++) & CLK_EN_MASK) + return 0; + if (clk->parent) + __clk_enable(clk->parent); + if (clk->secondary) + __clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + return 0; +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = __clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return; + if (clk->flags & ALWAYS_ENABLED) + return; + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + return clk->ref & CLK_EN_MASK; +} +EXPORT_SYMBOL(clk_get_usecount); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags, rate; + if (clk == NULL || IS_ERR(clk) || clk->get_rate == NULL) + return 0UL; + + spin_lock_irqsave(&clockfw_lock, flags); + rate = clk->get_rate(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk) || !clk->round_rate) + return 0; + + if (clk->flags & RATE_FIXED) + return 0; + + if (clk->round_rate) + return clk->round_rate(clk, rate); + return 0; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) + return ret; + + if (clk->flags & RATE_FIXED) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = clk->set_rate(clk, rate); + spin_unlock_irqrestore(&clockfw_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long flags; + int ret = -EINVAL; + struct clk *prev_parent; + + if (clk == NULL || IS_ERR(clk) || parent == NULL || + IS_ERR(parent) || clk->set_parent == NULL || + parent->get_rate == NULL) + return ret; + + if (clk->ref & CLK_EN_MASK) + clk_enable(parent); + + spin_lock_irqsave(&clockfw_lock, flags); + prev_parent = clk->parent; + ret = clk->set_parent(clk, parent); + if (ret) { + spin_unlock_irqrestore(&clockfw_lock, flags); + if (clk->ref & CLK_EN_MASK) + clk_disable(parent); + return ret; + } + + clk->parent = parent; + + spin_unlock_irqrestore(&clockfw_lock, flags); + + if (clk->ref & CLK_EN_MASK) + clk_disable(prev_parent); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + struct clk *ret = NULL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_register(struct clk_lookup *lookup) +{ + if (lookup == NULL || IS_ERR(lookup) || + lookup->clk == NULL || IS_ERR(lookup->clk)) + return -EINVAL; + + if (lookup->clk->ref & CLK_REF_LIMIT) + return -EEXIST; + + if (!(lookup->clk->enable)) + lookup->clk->enable = default_clk_enable; + if (!(lookup->clk->disable)) + lookup->clk->disable = default_clk_disable; + if (!(lookup->clk->get_rate)) + lookup->clk->get_rate = default_get_rate; + + clkdev_add(lookup); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk_lookup *lookup) +{ + if (lookup == NULL || IS_ERR(lookup) || + lookup->clk == NULL || IS_ERR(lookup->clk)) + return; + + if (lookup->clk->ref & CLK_REF_LIMIT) + return; + + clkdev_drop(lookup); + if (lookup->clk->enable == default_clk_enable) + lookup->clk->enable = NULL; + if (lookup->clk->disable == default_clk_disable) + lookup->clk->disable = NULL; + if (lookup->clk->get_rate == default_get_rate) + lookup->clk->get_rate = NULL; +} +EXPORT_SYMBOL(clk_unregister); diff --git a/arch/arm/plat-mxs/core.c b/arch/arm/plat-mxs/core.c new file mode 100644 index 000000000000..7f91808e6c66 --- /dev/null +++ b/arch/arm/plat-mxs/core.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/err.h> + +#include <asm/proc-fns.h> + +static void (*machine_arch_reset) (char mode, const char *cmd); + +void arch_idle(void) +{ + cpu_do_idle(); +} + +void arch_reset(char mode, const char *cmd) +{ + if (machine_arch_reset) + machine_arch_reset(mode, cmd); +} + +static int __mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= (1 << 31); /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & (1 << 30)) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 30)) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +int mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __mxs_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} diff --git a/arch/arm/plat-mxs/device.c b/arch/arm/plat-mxs/device.c new file mode 100644 index 000000000000..9c9c6222127f --- /dev/null +++ b/arch/arm/plat-mxs/device.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/bitops.h> +#include <linux/platform_device.h> + +#include <mach/device.h> + +static int mxs_device_num; +static int mxs_device_done; +static DEFINE_MUTEX(device_mutex); +static struct list_head mxs_device_level[] = { + LIST_HEAD_INIT(mxs_device_level[0]), + LIST_HEAD_INIT(mxs_device_level[1]), + LIST_HEAD_INIT(mxs_device_level[2]), + LIST_HEAD_INIT(mxs_device_level[3]), +}; + +void mxs_nop_release(struct device *dev) +{ + /* Nothing */ +} + +int mxs_add_devices(struct platform_device *pdev, int num, int level) +{ + int i, ret = -ENOMEM; + if (pdev == NULL || IS_ERR(pdev) || num <= 0) + return -EINVAL; + + if (level < 0) + level = 0; + else if (level >= ARRAY_SIZE(mxs_device_level)) + level = ARRAY_SIZE(mxs_device_level) - 1; + + mutex_lock(&device_mutex); + if (mxs_device_done) { + ret = 0; + for (i = 0; i < num; i++) + ret |= platform_device_register(pdev + i); + goto out; + } + + if ((mxs_device_num + num) > MXS_MAX_DEVICES) + goto out; + mxs_device_num += num; + for (i = 0; i < num; i++) + list_add_tail(&pdev[i].dev.devres_head, + &mxs_device_level[level]); + ret = 0; +out: + mutex_unlock(&device_mutex); + return ret; +} + +int mxs_add_device(struct platform_device *pdev, int level) +{ + return mxs_add_devices(pdev, 1, level); +} + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct platform_device mxs_duart = { + .name = "mxs-duart", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct platform_device mxs_dma[] = { + { + .name = "mxs-dma-apbh", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, + { + .name = "mxs-dma-apbx", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +static struct mxs_dev_lookup dev_lookup[] = { +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) + { + .name = "mxs-duart", + .size = 1, + .pdev = &mxs_duart, + }, +#endif +#if defined(CONFIG_MXS_DMA_ENGINE) + { + .name = "mxs-dma", + .size = ARRAY_SIZE(mxs_dma), + .pdev = mxs_dma, + }, +#endif +}; + +struct platform_device *mxs_get_device(char *name, int id) +{ + int i, j; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev = (struct platform_device *)-ENODEV; + if (name == NULL || id < 0 || IS_ERR(name)) + return (struct platform_device *)-EINVAL; + + mutex_lock(&device_mutex); + for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) { + lookup = &dev_lookup[i]; + if (!strcmp(name, lookup->name)) { + if (test_bit(0, &lookup->lock)) { + pdev = (struct platform_device *)-EBUSY; + break; + } + + if (id >= lookup->size) + break; + for (j = 0; j < lookup->size; j++) { + if (id == (lookup->pdev[j]).id) { + pdev = &lookup->pdev[j]; + break; + } + } + break; + } + + } + mutex_unlock(&device_mutex); + return pdev; +} + +struct mxs_dev_lookup *mxs_get_devices(char *name) +{ + int i; + struct mxs_dev_lookup *lookup; + if (name == NULL || IS_ERR(name)) + return (struct mxs_dev_lookup *)-EINVAL; + + mutex_lock(&device_mutex); + for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) { + lookup = &dev_lookup[i]; + if (!strcmp(name, lookup->name)) { + if (test_and_set_bit(0, &lookup->lock)) + lookup = (struct mxs_dev_lookup *)-EBUSY; + mutex_unlock(&device_mutex); + return lookup; + } + + } + mutex_unlock(&device_mutex); + return (struct mxs_dev_lookup *)-ENODEV; +} + +int mxs_device_init(void) +{ + int i, ret = 0; + struct list_head *p, *n; + struct device *dev; + struct platform_device *pdev; + mutex_lock(&device_mutex); + mxs_device_done = 1; + mutex_unlock(&device_mutex); + + for (i = 0; i < ARRAY_SIZE(mxs_device_level); i++) { + list_for_each_safe(p, n, mxs_device_level + i) { + dev = list_entry(p, struct device, devres_head); + list_del(p); + pdev = container_of(dev, struct platform_device, dev); + ret |= platform_device_register(pdev); + } + } + + return ret; +} + +device_initcall(mxs_device_init); diff --git a/arch/arm/plat-mxs/dma-apbh.c b/arch/arm/plat-mxs/dma-apbh.c new file mode 100644 index 000000000000..221ff491cbea --- /dev/null +++ b/arch/arm/plat-mxs/dma-apbh.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/dmapool.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <mach/device.h> +#include <mach/dmaengine.h> + +#include "regs-apbh.h" + +static int mxs_dma_apbh_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + + sem = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + sem = (sem & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBH_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBH_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBH_CHn_SEMA(chan)); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_CLR); + return 0; +} + +static void mxs_dma_apbh_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_SET); +} + +static void mxs_dma_apbh_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << (chan + BP_APBH_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void mxs_dma_apbh_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void +mxs_dma_apbh_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_CLR); +} + +static int +mxs_dma_apbh_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + return (reg & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbh_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_SET); + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL2_SET); + } else { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_CLR); + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL2_CLR); + } +} + +static int +mxs_dma_apbh_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBH_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbh_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbh = { + .name = "mxs-dma-apbh", + .enable = mxs_dma_apbh_enable, + .disable = mxs_dma_apbh_disable, + .reset = mxs_dma_apbh_reset, + .freeze = mxs_dma_apbh_freeze, + .unfreeze = mxs_dma_apbh_unfreeze, + .read_semaphore = mxs_dma_apbh_read_semaphore, + .enable_irq = mxs_dma_apbh_enable_irq, + .irq_is_pending = mxs_dma_apbh_irq_is_pending, + .ack_irq = mxs_dma_apbh_ack_irq, +}; + +static int __devinit dma_apbh_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbh.base = IO_ADDRESS(res->start); + __raw_writel(BM_APBH_CTRL0_SFTRST, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbh.base + HW_APBH_CTRL0_CLR) & + BM_APBH_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBH_CTRL0_CLKGATE, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + if (plat->burst8) + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + if (plat->burst) + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + mxs_dma_apbh.pdev = pdev; + mxs_dma_apbh.chan_base = plat->chan_base; + mxs_dma_apbh.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbh); + return mxs_dma_device_register(&mxs_dma_apbh); +} + +static int __devexit dma_apbh_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver dma_apbh_driver = { + .probe = dma_apbh_probe, + .remove = __devexit_p(dma_apbh_remove), + .driver = { + .name = "mxs-dma-apbh"}, +}; + +static int __init mxs_dma_apbh_init(void) +{ + return platform_driver_register(&dma_apbh_driver); +} + +fs_initcall(mxs_dma_apbh_init); diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c new file mode 100644 index 000000000000..40d299e9e812 --- /dev/null +++ b/arch/arm/plat-mxs/dma-apbx.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/dmapool.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <mach/device.h> +#include <mach/dmaengine.h> + +#include "regs-apbx.h" + +static int mxs_dma_apbx_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + sem = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan)); + sem = (sem & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBX_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBX_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBX_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBX_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBX_CHn_SEMA(chan)); + return 0; +} + +static void mxs_dma_apbx_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(0, pdev->base + HW_APBX_CHn_SEMA(chan)); +} + +static void mxs_dma_apbx_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << (chan + BP_APBX_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBX_CHANNEL_CTRL_SET); +} + +static void mxs_dma_apbx_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_SET); +} + +static void +mxs_dma_apbx_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_CLR); +} + +static int +mxs_dma_apbx_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan)); + return (reg & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbx_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_SET); + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL2_SET); + } else { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_CLR); + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL2_CLR); + } +} + +static int +mxs_dma_apbx_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBX_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBX_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbx_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBX_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbx = { + .name = "mxs-dma-apbx", + .enable = mxs_dma_apbx_enable, + .disable = mxs_dma_apbx_disable, + .reset = mxs_dma_apbx_reset, + .freeze = mxs_dma_apbx_freeze, + .unfreeze = mxs_dma_apbx_unfreeze, + .read_semaphore = mxs_dma_apbx_read_semaphore, + .enable_irq = mxs_dma_apbx_enable_irq, + .irq_is_pending = mxs_dma_apbx_irq_is_pending, + .ack_irq = mxs_dma_apbx_ack_irq, +}; + +static int __devinit dma_apbx_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbx.base = IO_ADDRESS(res->start); + __raw_writel(BM_APBX_CTRL0_SFTRST, + mxs_dma_apbx.base + HW_APBX_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbx.base + HW_APBX_CTRL0_CLR) & + BM_APBX_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBX_CTRL0_CLKGATE, + mxs_dma_apbx.base + HW_APBX_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + + mxs_dma_apbx.pdev = pdev; + mxs_dma_apbx.chan_base = plat->chan_base; + mxs_dma_apbx.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbx); + return mxs_dma_device_register(&mxs_dma_apbx); +} + +static int __devexit dma_apbx_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver dma_apbx_driver = { + .probe = dma_apbx_probe, + .remove = __devexit_p(dma_apbx_remove), + .driver = { + .name = "mxs-dma-apbx"}, +}; + +static int __init mxs_dma_apbx_init(void) +{ + return platform_driver_register(&dma_apbx_driver); +} + +fs_initcall(mxs_dma_apbx_init); diff --git a/arch/arm/plat-mxs/dmaengine.c b/arch/arm/plat-mxs/dmaengine.c new file mode 100644 index 000000000000..c3e592c1bdff --- /dev/null +++ b/arch/arm/plat-mxs/dmaengine.c @@ -0,0 +1,579 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/device.h> +#include <linux/dmapool.h> +#include <linux/proc_fs.h> +#include <linux/seq_file.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/io.h> + +#include <mach/dma.h> +#include <mach/dmaengine.h> + +static void *mxs_dma_pool; +static int mxs_dma_alignment = MXS_DMA_ALIGNMENT; +static DEFINE_MUTEX(mxs_dma_mutex); +static LIST_HEAD(mxs_dma_devices); +static struct mxs_dma_chan mxs_dma_channels[MAX_DMA_CHANNELS]; + +int mxs_dma_request(int channel, struct device *dev, const char *name) +{ + int ret = 0; + struct mxs_dma_chan *pchan; + + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + + if (!dev || !name) + return -EINVAL; + pchan = mxs_dma_channels + channel; + mutex_lock(&mxs_dma_mutex); + if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) { + ret = -ENODEV; + goto out; + } + if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) { + ret = -EBUSY; + goto out; + } + pchan->flags |= MXS_DMA_FLAGS_ALLOCATED; + pchan->name = name; + pchan->dev = (unsigned long)dev; + pchan->active_num = 0; + pchan->pending_num = 0; + spin_lock_init(&pchan->lock); + INIT_LIST_HEAD(&pchan->active); + INIT_LIST_HEAD(&pchan->done); +out: + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_request); + +void mxs_dma_release(int channel, struct device *dev) +{ + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + + if (pchan->dev != (unsigned long)dev) + return; + + mutex_lock(&mxs_dma_mutex); + pchan->dev = 0; + pchan->active_num = 0; + pchan->pending_num = 0; + pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED; + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_release); + +int mxs_dma_enable(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + pdma = pchan->dma; + mutex_lock(&mxs_dma_mutex); + spin_lock_irqsave(&pchan->lock, flags); + if (pchan->pending_num && pdma->enable) + ret = pdma->enable(pchan, channel - pdma->chan_base); + pchan->flags |= MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_enable); + +void mxs_dma_disable(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) + return; + pdma = pchan->dma; + mutex_lock(&mxs_dma_mutex); + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->disable) + pdma->disable(pchan, channel - pdma->chan_base); + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + pchan->active_num = 0; + pchan->pending_num = 0; + list_splice(&pchan->active, &pchan->done); + spin_unlock_irqrestore(&pchan->lock, flags); + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_disable); + +int mxs_dma_cooked(int channel, struct list_head *head) +{ + int sem; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct list_head *p, *q; + struct mxs_dma_desc *pdesc; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + sem = mxs_dma_read_semaphore(channel); + if (sem < 0) + return sem; + spin_lock_irqsave(&pchan->lock, flags); + list_for_each_safe(p, q, &pchan->active) { + if ((pchan->active_num) <= sem) + break; + pdesc = list_entry(p, struct mxs_dma_desc, node); + pdesc->flags &= ~MXS_DMA_DESC_READY; + if (head) + list_move_tail(p, head); + else + list_move_tail(p, &pchan->done); + pchan->active_num--; + } + if (sem == 0) + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + + BUG_ON(sem != pchan->active_num); + return 0; +} +EXPORT_SYMBOL(mxs_dma_cooked); + +void mxs_dma_reset(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->reset) + pdma->reset(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_reset); + +void mxs_dma_freeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->freeze) + pdma->freeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_freeze); + +void mxs_dma_unfreeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->unfreeze) + pdma->unfreeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_unfreeze); + +int mxs_dma_read_semaphore(int channel) +{ + int ret = -EINVAL; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->read_semaphore) + ret = pdma->read_semaphore(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_read_semaphore); + +void mxs_dma_enable_irq(int channel, int en) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->enable_irq) + pdma->enable_irq(pdma, channel - pdma->chan_base, en); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_enable_irq); + +int mxs_dma_irq_is_pending(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->irq_is_pending) + ret = pdma->irq_is_pending(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_irq_is_pending); + +void mxs_dma_ack_irq(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->ack_irq) + pdma->ack_irq(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_ack_irq); + +void mxs_dma_set_target(int channel, int target) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->set_target) + pdma->set_target(pdma, channel - pdma->chan_base, target); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_set_target); + +/* mxs dma utility function */ +struct mxs_dma_desc *mxs_dma_alloc_desc(void) +{ + struct mxs_dma_desc *pdesc; + unsigned int address; + if (mxs_dma_pool == NULL) + return NULL; + + pdesc = dma_pool_alloc(mxs_dma_pool, GFP_KERNEL, &address); + if (pdesc == NULL) + return NULL; + memset(pdesc, 0, sizeof(*pdesc)); + pdesc->address = address; + return pdesc; +}; +EXPORT_SYMBOL(mxs_dma_alloc_desc); + +void mxs_dma_free_desc(struct mxs_dma_desc *pdesc) +{ + if (pdesc == NULL) + return; + + if (mxs_dma_pool == NULL) + return; + + dma_pool_free(mxs_dma_pool, pdesc, pdesc->address); +} +EXPORT_SYMBOL(mxs_dma_free_desc); + +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_desc *last; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + pdma = pchan->dma; + pdesc->cmd.next = 0; + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + last = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + pdesc->cmd.next = last->cmd.next; + last->cmd.next = mxs_dma_cmd_address(pdesc); + if (pdesc->cmd.cmd.bits.chain) { + last->cmd.cmd.bits.chain = 1; + pdesc->cmd.cmd.bits.chain = 0; + } + } + pdesc->flags |= MXS_DMA_DESC_READY; + pchan->pending_num++; + list_add_tail(&pdesc->node, &pchan->active); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_append); + +int mxs_dma_desc_add_list(int channel, struct list_head *head) +{ + int ret = 0, size = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + struct list_head *p; + struct mxs_dma_desc *prev = NULL, *pcur; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (list_empty(head)) + return 0; + + pdma = pchan->dma; + list_for_each(p, head) { + pcur = list_entry(p, struct mxs_dma_desc, node); + if (prev) + prev->cmd.next = mxs_dma_cmd_address(pcur); + pcur->flags |= MXS_DMA_DESC_READY; + prev = pcur; + size++; + } + pcur = list_first_entry(head, struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + pcur = list_entry(pchan->active.next, + struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + pcur = list_first_entry(head, struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + } + list_splice(head, &pchan->active); + pchan->pending_num += size; + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_add_list); + +int mxs_dma_get_cooked(int channel, struct list_head *head) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (head == NULL) + return 0; + + spin_lock_irqsave(&pchan->lock, flags); + list_splice(&pchan->done, head); + spin_unlock_irqrestore(&pchan->lock, flags); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_cooked); + +int mxs_dma_device_register(struct mxs_dma_device *pdev) +{ + int i; + struct mxs_dma_chan *pchan; + + if (pdev == NULL || !pdev->chan_num) + return -EINVAL; + + if ((pdev->chan_base >= MAX_DMA_CHANNELS) || + ((pdev->chan_base + pdev->chan_num) > MAX_DMA_CHANNELS)) + return -EINVAL; + + mutex_lock(&mxs_dma_mutex); + pchan = mxs_dma_channels + pdev->chan_base; + for (i = 0; i < pdev->chan_num; i++, pchan++) { + pchan->dma = pdev; + pchan->flags = MXS_DMA_FLAGS_VALID; + } + list_add(&pdev->node, &mxs_dma_devices); + mutex_unlock(&mxs_dma_mutex); + return 0; +} +EXPORT_SYMBOL(mxs_dma_device_register); + +static int __init mxs_dma_alignment_setup(char *line) +{ + get_option(&line, &mxs_dma_alignment); + mxs_dma_alignment = (mxs_dma_alignment + 3) & (~3); + mxs_dma_alignment = max(mxs_dma_alignment, MXS_DMA_ALIGNMENT); + return 1; +}; + +__setup("mxs-dma-alignment=", mxs_dma_alignment_setup); + +static int mxs_dmaengine_init(void) +{ + mxs_dma_pool = dma_pool_create("mxs_dma", NULL, + sizeof(struct mxs_dma_desc), + mxs_dma_alignment, PAGE_SIZE); + if (mxs_dma_pool == NULL) + return -ENOMEM; + return 0; +} + +subsys_initcall(mxs_dmaengine_init); + +#ifdef CONFIG_PROC_FS + +static void *mxs_dma_proc_seq_start(struct seq_file *file, loff_t * index) +{ + if (*index >= MAX_DMA_CHANNELS) + return NULL; + return mxs_dma_channels + *index; +} + +static void *mxs_dma_proc_seq_next(struct seq_file *file, void *data, + loff_t *index) +{ + if (data == NULL) + return NULL; + + if (*index >= MAX_DMA_CHANNELS) + return NULL; + + return mxs_dma_channels + (*index)++; +} + +static void mxs_dma_proc_seq_stop(struct seq_file *file, void *data) +{ +} + +static int mxs_dma_proc_seq_show(struct seq_file *file, void *data) +{ + int result; + struct mxs_dma_chan *pchan = (struct mxs_dma_chan *)data; + struct mxs_dma_device *pdev = pchan->dma; + result = seq_printf(file, "%s-channel%-d (%s)\n", + pdev->name, + pchan - mxs_dma_channels, + pchan->name ? pchan->name : "idle"); + return result; +} + +static const struct seq_operations mxc_dma_proc_seq_ops = { + .start = mxs_dma_proc_seq_start, + .next = mxs_dma_proc_seq_next, + .stop = mxs_dma_proc_seq_stop, + .show = mxs_dma_proc_seq_show +}; + +static int mxs_dma_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &mxc_dma_proc_seq_ops); +} + +static const struct file_operations mxs_dma_proc_info_ops = { + .open = mxs_dma_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init mxs_dmaengine_info_init(void) +{ + struct proc_dir_entry *res; + res = create_proc_entry("dma-engine", 0, NULL); + if (!res) { + printk(KERN_ERR "Failed to create dma info file \n"); + return -ENOMEM; + } + res->proc_fops = &mxs_dma_proc_info_ops; + return 0; +} + +late_initcall(mxs_dmaengine_info_init); +#endif diff --git a/arch/arm/plat-mxs/gpio.c b/arch/arm/plat-mxs/gpio.c new file mode 100644 index 000000000000..f12d417b03e9 --- /dev/null +++ b/arch/arm/plat-mxs/gpio.c @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/gpio.h> +#include <linux/list.h> +#include <linux/irq.h> + +#include <mach/hardware.h> +#include <mach/pinctrl.h> + +#if MXS_ARCH_NR_GPIOS % PINS_PER_BANK +#error "MXS_ARCH_NR_GPIOS must be multipled of PINS_PER_BANK" +#endif + +static struct mxs_gpio_port *mxs_gpios[MXS_ARCH_NR_GPIOS / PINS_PER_BANK]; + +static inline int mxs_valid_gpio(struct mxs_gpio_port *port) +{ + struct mxs_gpio_chip *chip = port->chip; + + if (port->id >= (MXS_ARCH_NR_GPIOS / PINS_PER_BANK)) + return -EINVAL; + + if (port->irq < 0 && port->child_irq > 0) + return -EINVAL; + if (chip->get == NULL || chip->set == NULL || chip->set_dir == NULL) + return -EINVAL; + if (port->child_irq > 0) { + if (chip->get_irq_stat == NULL) + return -EINVAL; + if (chip->mask_irq == NULL || chip->unmask_irq == NULL) + return -EINVAL; + } + return 0; +} + +static int mxs_gpio_request(struct gpio_chip *chip, unsigned int pin) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return mxs_request_pin(MXS_PIN_ENCODE(port->id, pin), + PIN_GPIO, GPIO_ID_NAME); +} + +static void mxs_gpio_free(struct gpio_chip *chip, unsigned int pin) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return mxs_release_pin(MXS_PIN_ENCODE(port->id, pin), GPIO_ID_NAME); +} + +static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + if (port->child_irq < 0) + return -ENXIO; + return port->child_irq + index; +} + +static int mxs_gpio_get(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return port->chip->get(port, index); +} + +static void mxs_gpio_set(struct gpio_chip *chip, unsigned int index, int v) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + port->chip->set(port, index, v); +} + +static int mxs_gpio_output(struct gpio_chip *chip, unsigned int index, int v) +{ + int ret; + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + ret = port->chip->set_dir(port, index, 0); + if (!ret) + port->chip->set(port, index, v); + return ret; +} + +static int mxs_gpio_input(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return port->chip->set_dir(port, index, 1); +} + +static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + struct mxs_gpio_port *port = get_irq_data(irq); + int gpio_irq = port->child_irq; + u32 irq_stat = port->chip->get_irq_stat(port); + + desc->chip->mask(irq); + + while (irq_stat) { + if (irq_stat & 1) + generic_handle_irq(gpio_irq); + gpio_irq++; + irq_stat >>= 1; + } + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +static int mxs_gpio_set_irq_type(unsigned int irq, unsigned int type) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return -ENXIO; + if (port->chip->set_irq_type) + return port->chip->set_irq_type(port, GPIO_TO_PINS(gpio), type); + return -ENODEV; +} + +static void mxs_gpio_ack_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + if (port->chip->ack_irq) + port->chip->ack_irq(port, GPIO_TO_PINS(gpio)); +} + +static void mxs_gpio_mask_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + port->chip->mask_irq(port, GPIO_TO_PINS(gpio)); +} + +static void mxs_gpio_unmask_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + port->chip->unmask_irq(port, GPIO_TO_PINS(gpio)); +} + +static struct irq_chip gpio_irq_chip = { + .ack = mxs_gpio_ack_irq, + .mask = mxs_gpio_mask_irq, + .unmask = mxs_gpio_unmask_irq, + .set_type = mxs_gpio_set_irq_type, +}; + +int __init mxs_add_gpio_port(struct mxs_gpio_port *port) +{ + int i, ret; + if (!(port && port->chip)) + return -EINVAL; + + if (mxs_valid_gpio(port)) + return -EINVAL; + + if (mxs_gpios[port->id]) + return -EBUSY; + + mxs_gpios[port->id] = port; + + port->port.base = port->id * PINS_PER_BANK; + port->port.ngpio = PINS_PER_BANK; + port->port.can_sleep = 1; + port->port.exported = 1; + port->port.to_irq = mxs_gpio_to_irq; + port->port.direction_input = mxs_gpio_input; + port->port.direction_output = mxs_gpio_output; + port->port.get = mxs_gpio_get; + port->port.set = mxs_gpio_set; + port->port.request = mxs_gpio_request; + port->port.free = mxs_gpio_free; + port->port.owner = THIS_MODULE; + ret = gpiochip_add(&port->port); + if (ret < 0) + return ret; + + if (port->child_irq < 0) + return 0; + + for (i = 0; i < PINS_PER_BANK; i++) { + gpio_irq_chip.mask(port->child_irq + i); + set_irq_chip(port->child_irq + i, &gpio_irq_chip); + set_irq_handler(port->child_irq + i, handle_level_irq); + set_irq_flags(port->child_irq + i, IRQF_VALID); + } + set_irq_chained_handler(port->irq, mxs_gpio_irq_handler); + set_irq_data(port->irq, port); + return ret; +}; diff --git a/arch/arm/plat-mxs/icoll.c b/arch/arm/plat-mxs/icoll.c new file mode 100644 index 000000000000..ef05e63d3dd1 --- /dev/null +++ b/arch/arm/plat-mxs/icoll.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/delay.h> + +#include <mach/hardware.h> +#include <mach/device.h> + +#include "regs-icoll.h" + +void __iomem *g_icoll_base; + +/* + * IRQ handling + */ +static void icoll_ack_irq(unsigned int irq) +{ + __raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR); + + /* ACK current interrupt */ + __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, + g_icoll_base + HW_ICOLL_LEVELACK); + + /* Barrier */ + (void)__raw_readl(g_icoll_base + HW_ICOLL_STAT); +} + +static void icoll_mask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + g_icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq)); +} + +static void icoll_unmask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + g_icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); +} + +static struct irq_chip icoll_chip = { + .ack = icoll_ack_irq, + .mask = icoll_mask_irq, + .unmask = icoll_unmask_irq, +}; + +void __init avic_init_irq(void __iomem *base, int nr_irqs) +{ + int i; + g_icoll_base = base; + + /* Reset icoll */ + __raw_writel(BM_ICOLL_CTRL_SFTRST, g_icoll_base + HW_ICOLL_CTRL_CLR); + + for (i = 0; i < 100000; i++) { + if (!(__raw_readl(g_icoll_base + HW_ICOLL_CTRL) & + BM_ICOLL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 100000) { + printk(KERN_ERR "%s:%d timeout when enableing\n", + __func__, __LINE__); + return; + } + __raw_writel(BM_ICOLL_CTRL_CLKGATE, g_icoll_base + HW_ICOLL_CTRL_CLR); + + for (i = 0; i < nr_irqs; i++) { + __raw_writel(0, g_icoll_base + HW_ICOLL_INTERRUPTn(i)); + set_irq_chip(i, &icoll_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3), + g_icoll_base + HW_ICOLL_LEVELACK); + + __raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR); + /* Barrier */ + (void)__raw_readl(g_icoll_base + HW_ICOLL_STAT); +} diff --git a/arch/arm/plat-mxs/include/mach/clkdev.h b/arch/arm/plat-mxs/include/mach/clkdev.h new file mode 100644 index 000000000000..d6a82c8d5782 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clkdev.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +extern int __clk_get(struct clk *clk); +extern void __clk_put(struct clk *clk); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/clock.h b/arch/arm/plat-mxs/include/mach/clock.h new file mode 100644 index 000000000000..4eae0f85e3b7 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clock.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H +#define __ASM_ARM_ARCH_CLOCK_H + +#ifndef __ASSEMBLER__ + +#include <linux/list.h> +#include <asm/clkdev.h> + +struct clk { + int id; + struct clk *parent; + struct clk *secondary; + unsigned long flags; + + unsigned int ref; + unsigned int scale_bits; + unsigned int enable_bits; + unsigned int bypass_bits; + unsigned int busy_bits; + + unsigned int wait:1; + unsigned int invert:1; + + void __iomem *enable_reg; + void __iomem *scale_reg; + void __iomem *bypass_reg; + void __iomem *busy_reg; + + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to get the clock rate. + */ + unsigned long (*get_rate) (struct clk *); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +int clk_get_usecount(struct clk *clk); +extern int clk_register(struct clk_lookup *lookup); +extern void clk_unregister(struct clk_lookup *lookup); + +static inline int clk_is_busy(struct clk *clk) +{ + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); +} + +/* Clock flags */ +/* 0 ~ 16 attribute flags */ +#define ALWAYS_ENABLED (1 << 0) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ + +/* 16 ~ 23 reservied */ +/* 24 ~ 31 run time flags */ + +#define CLK_REF_UNIT 0x00010000 +#define CLK_REF_LIMIT 0xFFFF0000 +#define CLK_EN_MASK 0x0000FFFF +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h new file mode 100644 index 000000000000..2debcc89ffec --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/device.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DEVICE_H +#define __ASM_ARM_ARCH_DEVICE_H + +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/ioport.h> + +#include <asm/mach/time.h> + +#define MXS_MAX_DEVICES 128 + +struct mxs_sys_timer { + struct sys_timer timer; + unsigned char id; + unsigned char clk_sel; + unsigned char resv[2]; + int irq; + struct clk *clk; + void __iomem *base; +}; + +struct mxs_dev_lookup { + char *name; + unsigned long lock; + int size; + struct platform_device *pdev; +}; + +/* Define the Platform special structure for each device type*/ +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; + +extern void mxs_timer_init(struct mxs_sys_timer *timer); + +extern void mxs_nop_release(struct device *dev); +extern int mxs_add_devices(struct platform_device *, int num, int level); +extern int mxs_add_device(struct platform_device *, int level); +extern struct platform_device *mxs_get_device(char *name, int id); +extern struct mxs_dev_lookup *mxs_get_devices(char *name); + +#ifdef CONFIG_MXS_ICOLL +extern void __init avic_init_irq(void __iomem *base, int nr_irqs); +#endif + +#endif diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h new file mode 100644 index 000000000000..7d7ab696f32f --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/dmaengine.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int resv:2; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + unsigned long address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 + /* address is desc physcial address */ + dma_addr_t address; + /* buffer address */ + void *buffer; + struct list_head node; +}; + +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/* dma controller devices */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/* request a dma channel */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); +/* Release a dma channel */ +extern void mxs_dma_release(int channel, struct device *dev); + +/* Enable dma transfer */ +extern int mxs_dma_enable(int channel); + +/* + * Disable dma transfer and the desc will be putted into done list + * Before calling mxs_dma_release, mxs_dma_get_cooked must called to + * take dma desc back. + */ +extern void mxs_dma_disable(int channel); +/* reset dma channel */ +extern void mxs_dma_reset(int channel); +/* freeze dma channel */ +extern void mxs_dma_freeze(int channel); +/* unfreeze dma channel */ +extern void mxs_dma_unfreeze(int channel); +/* + * Called to task back the done desc. if head is NULL, they will be + * put into done list. And must called mxs_dma_get_cooked to take + * them back + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/* Read the dma semaphore to check if there are pending dma desc */ +extern int mxs_dma_read_semaphore(int channel); +/* check dma irq is pending */ +extern int mxs_dma_irq_is_pending(int channel); +/* enable or disable dma irq */ +extern void mxs_dma_enable_irq(int channel, int en); +/* clear dma irq */ +extern void mxs_dma_ack_irq(int channel); + +/* Used to configure channel related device selection:NOUSED in i.MX28 */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/* Add a dma desc to channel*/ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); +/* Add a list of dma desc to channel*/ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); +/* Take the working done desc back */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); +#endif diff --git a/arch/arm/plat-mxs/include/mach/entry-macro.S b/arch/arm/plat-mxs/include/mach/entry-macro.S new file mode 100644 index 000000000000..353a7b2cc8fd --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/entry-macro.S @@ -0,0 +1,36 @@ +/* + * Low-level IRQ helper macros for Freescale MXS-based + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =g_icoll_base + ldr \base, [\base] + ldr \irqnr, [\base, #0x70] + cmp \irqnr, #0x7F + moveqs \irqnr, #0 + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/plat-mxs/include/mach/gpio.h b/arch/arm/plat-mxs/include/mach/gpio.h new file mode 100644 index 000000000000..7b634149ec23 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <mach/hardware.h> +#include <asm-generic/gpio.h> + +#define GPIO_ID_NAME "gpio" +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq +#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) + +struct mxs_gpio_port; +struct mxs_gpio_chip { + int (*set_dir) (struct mxs_gpio_port *, int, unsigned int); + int (*get) (struct mxs_gpio_port *, int); + void (*set) (struct mxs_gpio_port *, int, int); + unsigned int (*get_irq_stat) (struct mxs_gpio_port *); + int (*set_irq_type) (struct mxs_gpio_port *, int, unsigned int); + void (*unmask_irq) (struct mxs_gpio_port *, int); + void (*mask_irq) (struct mxs_gpio_port *, int); + void (*ack_irq) (struct mxs_gpio_port *, int); +}; + +struct mxs_gpio_port { + int id; + int irq; + int child_irq; + struct mxs_gpio_chip *chip; + struct gpio_chip port; +}; + +extern int mxs_add_gpio_port(struct mxs_gpio_port *port); + +static inline void +mxs_set_gpio_chip(struct mxs_gpio_port *port, struct mxs_gpio_chip *chip) +{ + if (port && chip) + port->chip = chip; +} + +#endif /* __ASM_ARCH_GPIO_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/hardware.h b/arch/arm/plat-mxs/include/mach/hardware.h new file mode 100644 index 000000000000..7fdbd054bf41 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/hardware.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_HARDWARE_H +#define __ASM_ARM_ARCH_HARDWARE_H + +#ifdef CONFIG_ARCH_MX28 +# include <mach/mx28.h> +# define cpu_is_mx28() 1 +# else +# define cpu_is_mx28() 0 +#endif + +#ifndef MXS_EXTEND_IRQS +#define MXS_EXTEND_IRQS 0 +#endif + +#ifndef MXS_ARCH_NR_GPIOS +#define MXS_ARCH_NR_GPIOS 160 +#endif + +#ifndef MXS_EXTEND_NR_GPIOS +#define MXS_EXTEND_NR_GPIOS 0 +#endif + +#define ARCH_NR_GPIOS (MXS_ARCH_NR_GPIOS + MXS_EXTEND_NR_GPIOS) + +#define MXS_GPIO_IRQ_START ARCH_NR_IRQS +#define MXS_EXTEND_IRQ_START (ARCH_NR_IRQS + ARCH_NR_GPIOS) + +#endif /* __ASM_ARM_ARCH_HARDWARE_H */ diff --git a/arch/arm/plat-mxs/include/mach/io.h b/arch/arm/plat-mxs/include/mach/io.h new file mode 100644 index 000000000000..7dff55ef7f12 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/io.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#define SET_REGISTER 0x4 +#define CLR_REGISTER 0x8 +#define TOG_REGISTER 0xC + +struct mxs_io_bank { + unsigned int raw; + unsigned int set; + unsigned int clr; + unsigned int tog; +}; +#endif diff --git a/arch/arm/plat-mxs/include/mach/irqs.h b/arch/arm/plat-mxs/include/mach/irqs.h new file mode 100644 index 000000000000..f2de0d22ad41 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/irqs.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#include <mach/hardware.h> + +#define NR_IRQS (ARCH_NR_IRQS + ARCH_NR_GPIOS + MXS_EXTEND_IRQS) + +#ifndef __ASSEMBLY__ +struct irq_ic_info { + unsigned int id_val; + unsigned int id_mask; + const char *name; + unsigned int base; +}; + +#define __irq_ic_info_attr __attribute__((__section__(".irq_ic_info.array"))) + +extern struct irq_ic_info *current_irq_ic_info; +#endif +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/memory.h b/arch/arm/plat-mxs/include/mach/memory.h new file mode 100644 index 000000000000..79c86db78d49 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/memory.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include <asm/page.h> +#include <asm/sizes.h> + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x40000000) + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DMA_ZONE_SIZE +#define MXS_DMA_ZONE_SIZE ((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT) +#else +#define MXS_DMA_ZONE_SIZE ((12 * SZ_1M) >> PAGE_SHIFT) +#endif + +static inline void __arch_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + if (node != 0) + return; + /* Create separate zone to reserve memory for DMA */ + zone_size[1] = zone_size[0] - MXS_DMA_ZONE_SIZE; + zone_size[0] = MXS_DMA_ZONE_SIZE; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +#define arch_adjust_zones(node, size, holes) \ + __arch_adjust_zones(node, size, holes) + +#endif +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#define ISA_DMA_THRESHOLD (0x0003ffffULL) + +#define CONSISTENT_DMA_SIZE SZ_32M + +#endif diff --git a/arch/arm/plat-mxs/include/mach/pinctrl.h b/arch/arm/plat-mxs/include/mach/pinctrl.h new file mode 100644 index 000000000000..3299e4280b90 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/pinctrl.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_PINCTRL_H +#define __ASM_ARM_ARCH_PINCTRL_H + +#include <linux/types.h> +#include <linux/gpio.h> + +#define PINS_PER_BANK 32 +#define GPIO_TO_PINS(gpio) ((gpio) % 32) +#define GPIO_TO_BANK(gpio) ((gpio) / 32) + +#define MXS_PIN_TO_GPIO(p) (((p) & MXS_PIN_PINID_MAX) |\ + ((((p) >> MXS_PIN_BANK_BIT) &\ + MXS_PIN_BANK_MAX) * PINS_PER_BANK)) + +#define MXS_PIN_BANK_BIT 24 +#define MXS_PIN_BANK_MAX (0x7FFFFFFF >> (MXS_PIN_BANK_BIT - 1)) +#define MXS_PIN_PINID_MAX ((1 << MXS_PIN_BANK_BIT) - 1) +#define MXS_PIN_TO_BANK(p) (((p) >> MXS_PIN_BANK_BIT) & MXS_PIN_BANK_MAX) +#define MXS_PIN_TO_PINID(p) ((p) & MXS_PIN_PINID_MAX) + +#define MXS_PIN_ENCODE(b, p) \ + ((((b) & MXS_PIN_BANK_MAX) << MXS_PIN_BANK_BIT) |\ + ((p) & MXS_PIN_PINID_MAX)) + +#define MXS_GPIO_MASK 0x7FFFFFFF +#define MXS_NON_GPIO 0x80000000 +/* + * Each pin may be routed up to four different HW interfaces + * including GPIO + */ +enum pin_fun { + PIN_FUN1 = 0, + PIN_FUN2, + PIN_FUN3, + PIN_GPIO, +}; + +/* + * Each pin may have different output drive strength in range from + * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. + */ +enum pad_strength { + PAD_4MA = 0, + PAD_8MA, + PAD_12MA, + PAD_RESV, + PAD_CLEAR = PAD_RESV, +}; + +/* + * Each pin can be programmed for 1.8V or 3.3V + */ +enum pad_voltage { + PAD_1_8V = 0, + PAD_3_3V, +}; + +/* + * Structure to define a group of pins and their parameters + */ +struct pin_desc { + char *name; + unsigned int id; + enum pin_fun fun; + enum pad_strength strength; + enum pad_voltage voltage; + unsigned pullup:1; + unsigned drive:1; + unsigned pull:1; + unsigned input:1; + unsigned data:1; +}; + +struct pin_bank { + const char *lable[sizeof(long) * 8]; + unsigned long id; + struct pinctrl_chip *chip; + unsigned long bitmap; + unsigned long gpio_port; +}; + +struct pinctrl_chip { + char *name; + unsigned int nouse; + unsigned int bank_size; + struct pin_bank *banks; + /* OPS */ + int (*pin2id) (struct pinctrl_chip *, unsigned int, unsigned int *); + unsigned int (*get_gpio) (struct pin_bank *, unsigned int); + void (*set_strength) (struct pin_bank *, unsigned int, + enum pad_strength); + void (*set_voltage) (struct pin_bank *, unsigned int, enum pad_voltage); + void (*set_pullup) (struct pin_bank *, unsigned int, int); + void (*set_type) (struct pin_bank *, unsigned int, enum pin_fun); +}; + +extern int __init mxs_set_pinctrl_chip(struct pinctrl_chip *); + +extern unsigned int mxs_pin2gpio(unsigned int); +extern int mxs_request_pin(unsigned int, enum pin_fun, const char *); +extern int mxs_set_type(unsigned int, enum pin_fun, const char *); +extern int mxs_set_strength(unsigned int, enum pad_strength, const char *); +extern int mxs_set_voltage(unsigned int, enum pad_voltage, const char *); +extern int mxs_set_pullup(unsigned int, int, const char *); +extern void mxs_release_pin(unsigned int, const char *); +#endif diff --git a/arch/arm/plat-mxs/include/mach/system.h b/arch/arm/plat-mxs/include/mach/system.h new file mode 100644 index 000000000000..d777723fedf3 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/system.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_SYSTEM_H__ +#define __ASM_ARCH_SYSTEM_H__ + +extern void arch_idle(void); + +void arch_reset(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); + +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h new file mode 100644 index 000000000000..9db3d688223a --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/timex.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * System time clock is sourced from the 32k clock + */ +#define CLOCK_TICK_RATE 32768 diff --git a/arch/arm/plat-mxs/include/mach/uncompress.h b/arch/arm/plat-mxs/include/mach/uncompress.h new file mode 100644 index 000000000000..fd4e4f845472 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/uncompress.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_PLAT_UNCOMPRESS_H +#define __ASM_PLAT_UNCOMPRESS_H + +#include <mach/hardware.h> + +/* + * Register includes are for when the MMU enabled; we need to define our + * own stuff here for pre-MMU use + */ +#define UART_PORT_BASE DUART_PHYS_ADDR +#define UART(c) (((volatile unsigned *)UART_PORT_BASE)[c]) + +/* + * This does not append a newline + */ +static void putc(char c) +{ + /* Wait for TX fifo empty */ + while ((UART(6) & (1 << 7)) == 0) + continue; + + /* Write byte */ + UART(0) = c; + + /* Wait for last bit to exit the UART */ + while (UART(6) & (1 << 3)) + continue; +} + +#define flush() do { } while (0) +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-mxs/include/mach/vmalloc.h b/arch/arm/plat-mxs/include/mach/vmalloc.h new file mode 100644 index 000000000000..cc6d5cf3133a --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define VMALLOC_END (0xF0000000) diff --git a/arch/arm/plat-mxs/pinctrl.c b/arch/arm/plat-mxs/pinctrl.c new file mode 100644 index 000000000000..658aa059fca4 --- /dev/null +++ b/arch/arm/plat-mxs/pinctrl.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/bitops.h> +#include <linux/gpio.h> +#include <linux/irq.h> + +#include <mach/pinctrl.h> + +static struct pinctrl_chip *g_chip; + +int mxs_request_pin(unsigned int pin, enum pin_fun fun, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + if (test_and_set_bit(index, &pb->bitmap)) + return -EBUSY; + pb->lable[index] = lab; + if (g_chip->set_type) + g_chip->set_type(pb, index, fun); + return 0; +} +EXPORT_SYMBOL(mxs_request_pin); + +int mxs_set_type(unsigned int pin, enum pin_fun fun, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->lable[index]) /* lable is const string */ + return -EINVAL; + if (g_chip->set_type) + g_chip->set_type(pb, index, fun); + return 0; +} +EXPORT_SYMBOL(mxs_set_type); + +int mxs_set_strength(unsigned int pin, enum pad_strength cfg, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->lable[index]) /* lable is const string */ + return -EINVAL; + if (g_chip->set_strength) + g_chip->set_strength(pb, index, cfg); + return 0; +} +EXPORT_SYMBOL(mxs_set_strength); + +int mxs_set_voltage(unsigned int pin, enum pad_voltage cfg, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->lable[index]) /* lable is const string */ + return -EINVAL; + if (g_chip->set_voltage) + g_chip->set_voltage(pb, index, cfg); + return 0; +} +EXPORT_SYMBOL(mxs_set_voltage); + +int mxs_set_pullup(unsigned int pin, int en, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->lable[index]) /* lable is const string */ + return -EINVAL; + if (g_chip->set_pullup) + g_chip->set_pullup(pb, index, en); + return 0; +} +EXPORT_SYMBOL(mxs_set_pullup); + +void mxs_release_pin(unsigned int pin, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return; + if (lab != pb->lable[index]) /* lable is const string */ + return; + pb->lable[index] = NULL; + + clear_bit(index, &pb->bitmap); +} +EXPORT_SYMBOL(mxs_release_pin); + +unsigned int mxs_pin2gpio(unsigned int pin) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + if (!g_chip->get_gpio) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + return g_chip->get_gpio(pb, index); +} + +int __init mxs_set_pinctrl_chip(struct pinctrl_chip *chip) +{ + if (!(chip && chip->banks && chip->bank_size && + chip->get_gpio && chip->pin2id)) + return -EINVAL; + + if (g_chip) + return -EEXIST; + g_chip = chip; + return 0; +}; diff --git a/arch/arm/plat-mxs/regs-apbh.h b/arch/arm/plat-mxs/regs-apbh.h new file mode 100644 index 000000000000..23f26ca10e9e --- /dev/null +++ b/arch/arm/plat-mxs/regs-apbh.h @@ -0,0 +1,535 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2 + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/plat-mxs/regs-apbx.h b/arch/arm/plat-mxs/regs-apbx.h new file mode 100644 index 000000000000..f788f1303ece --- /dev/null +++ b/arch/arm/plat-mxs/regs-apbx.h @@ -0,0 +1,433 @@ +/* + * Freescale APBX Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBX_H +#define __ARCH_ARM___APBX_H + +#define HW_APBX_CTRL0 (0x00000000) +#define HW_APBX_CTRL0_SET (0x00000004) +#define HW_APBX_CTRL0_CLR (0x00000008) +#define HW_APBX_CTRL0_TOG (0x0000000c) + +#define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BP_APBX_CTRL0_RSVD0 0 +#define BM_APBX_CTRL0_RSVD0 0x3FFFFFFF +#define BF_APBX_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_APBX_CTRL0_RSVD0) + +#define HW_APBX_CTRL1 (0x00000010) +#define HW_APBX_CTRL1_SET (0x00000014) +#define HW_APBX_CTRL1_CLR (0x00000018) +#define HW_APBX_CTRL1_TOG (0x0000001c) + +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBX_CTRL2 (0x00000020) +#define HW_APBX_CTRL2_SET (0x00000024) +#define HW_APBX_CTRL2_CLR (0x00000028) +#define HW_APBX_CTRL2_TOG (0x0000002c) + +#define BM_APBX_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBX_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBX_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBX_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBX_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBX_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBX_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBX_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBX_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBX_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBX_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBX_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBX_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBX_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBX_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBX_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBX_CHANNEL_CTRL (0x00000030) +#define HW_APBX_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBX_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBX_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBX_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_RX 0x0001 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_TX 0x0002 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF0 0x0010 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1 0x0020 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C0 0x0040 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C1 0x0080 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x0400 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x0800 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_RX 0x1000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_TX 0x2000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_RX 0x4000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_TX 0x8000 +#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_RX 0x0001 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_TX 0x0002 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF0 0x0010 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1 0x0020 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C0 0x0040 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C1 0x0080 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x0400 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x0800 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_RX 0x1000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_TX 0x2000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_RX 0x4000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_TX 0x8000 + +#define HW_APBX_DEVSEL (0x00000040) +#define HW_APBX_DEVSEL_SET (0x00000044) +#define HW_APBX_DEVSEL_CLR (0x00000048) +#define HW_APBX_DEVSEL_TOG (0x0000004c) + +#define BP_APBX_DEVSEL_CH15 30 +#define BM_APBX_DEVSEL_CH15 0xC0000000 +#define BF_APBX_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBX_DEVSEL_CH15) +#define BP_APBX_DEVSEL_CH14 28 +#define BM_APBX_DEVSEL_CH14 0x30000000 +#define BF_APBX_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBX_DEVSEL_CH14) +#define BP_APBX_DEVSEL_CH13 26 +#define BM_APBX_DEVSEL_CH13 0x0C000000 +#define BF_APBX_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBX_DEVSEL_CH13) +#define BP_APBX_DEVSEL_CH12 24 +#define BM_APBX_DEVSEL_CH12 0x03000000 +#define BF_APBX_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBX_DEVSEL_CH12) +#define BP_APBX_DEVSEL_CH11 22 +#define BM_APBX_DEVSEL_CH11 0x00C00000 +#define BF_APBX_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBX_DEVSEL_CH11) +#define BP_APBX_DEVSEL_CH10 20 +#define BM_APBX_DEVSEL_CH10 0x00300000 +#define BF_APBX_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBX_DEVSEL_CH10) +#define BP_APBX_DEVSEL_CH9 18 +#define BM_APBX_DEVSEL_CH9 0x000C0000 +#define BF_APBX_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBX_DEVSEL_CH9) +#define BP_APBX_DEVSEL_CH8 16 +#define BM_APBX_DEVSEL_CH8 0x00030000 +#define BF_APBX_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBX_DEVSEL_CH8) +#define BP_APBX_DEVSEL_CH7 14 +#define BM_APBX_DEVSEL_CH7 0x0000C000 +#define BF_APBX_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBX_DEVSEL_CH7) +#define BP_APBX_DEVSEL_CH6 12 +#define BM_APBX_DEVSEL_CH6 0x00003000 +#define BF_APBX_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBX_DEVSEL_CH6) +#define BP_APBX_DEVSEL_CH5 10 +#define BM_APBX_DEVSEL_CH5 0x00000C00 +#define BF_APBX_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBX_DEVSEL_CH5) +#define BP_APBX_DEVSEL_CH4 8 +#define BM_APBX_DEVSEL_CH4 0x00000300 +#define BF_APBX_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBX_DEVSEL_CH4) +#define BP_APBX_DEVSEL_CH3 6 +#define BM_APBX_DEVSEL_CH3 0x000000C0 +#define BF_APBX_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBX_DEVSEL_CH3) +#define BP_APBX_DEVSEL_CH2 4 +#define BM_APBX_DEVSEL_CH2 0x00000030 +#define BF_APBX_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBX_DEVSEL_CH2) +#define BP_APBX_DEVSEL_CH1 2 +#define BM_APBX_DEVSEL_CH1 0x0000000C +#define BF_APBX_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBX_DEVSEL_CH1) +#define BP_APBX_DEVSEL_CH0 0 +#define BM_APBX_DEVSEL_CH0 0x00000003 +#define BF_APBX_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBX_DEVSEL_CH0) + +/* + * multi-register-define name HW_APBX_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT) +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS) +#define BP_APBX_CHn_CMD_RSVD1 10 +#define BM_APBX_CHn_CMD_RSVD1 0x00000C00 +#define BF_APBX_CHn_CMD_RSVD1(v) \ + (((v) << 10) & BM_APBX_CHn_CMD_RSVD1) +#define BM_APBX_CHn_CMD_TERMINATEFLUSH 0x00000200 +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BP_APBX_CHn_CMD_RSVD0 4 +#define BM_APBX_CHn_CMD_RSVD0 0x00000030 +#define BF_APBX_CHn_CMD_RSVD0(v) \ + (((v) << 4) & BM_APBX_CHn_CMD_RSVD0) +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BF_APBX_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBX_CHn_CMD_COMMAND) +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 + +/* + * multi-register-define name HW_APBX_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBX_CHn_BAR_ADDRESS 0 +#define BM_APBX_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBX_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBX_CHn_SEMA_RSVD2 24 +#define BM_APBX_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBX_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBX_CHn_SEMA_RSVD2) +#define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBX_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBX_CHn_SEMA_PHORE) +#define BP_APBX_CHn_SEMA_RSVD1 8 +#define BM_APBX_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBX_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBX_CHn_SEMA_RSVD1) +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBX_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBX_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBX_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBX_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBX_CHn_DEBUG1_END 0x10000000 +#define BP_APBX_CHn_DEBUG1_RSVD2 25 +#define BM_APBX_CHn_DEBUG1_RSVD2 0x0E000000 +#define BF_APBX_CHn_DEBUG1_RSVD2(v) \ + (((v) << 25) & BM_APBX_CHn_DEBUG1_RSVD2) +#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBX_CHn_DEBUG1_RSVD1 5 +#define BM_APBX_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBX_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBX_CHn_DEBUG1_RSVD1) +#define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG1_STATEMACHINE) +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E + +/* + * multi-register-define name HW_APBX_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBX_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBX_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBX_CHn_DEBUG2_APB_BYTES) +#define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBX_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBX_VERSION (0x00000800) + +#define BP_APBX_VERSION_MAJOR 24 +#define BM_APBX_VERSION_MAJOR 0xFF000000 +#define BF_APBX_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBX_VERSION_MAJOR) +#define BP_APBX_VERSION_MINOR 16 +#define BM_APBX_VERSION_MINOR 0x00FF0000 +#define BF_APBX_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBX_VERSION_MINOR) +#define BP_APBX_VERSION_STEP 0 +#define BM_APBX_VERSION_STEP 0x0000FFFF +#define BF_APBX_VERSION_STEP(v) \ + (((v) << 0) & BM_APBX_VERSION_STEP) +#endif /* __ARCH_ARM___APBX_H */ diff --git a/arch/arm/plat-mxs/regs-icoll.h b/arch/arm/plat-mxs/regs-icoll.h new file mode 100644 index 000000000000..f06ac0d4720b --- /dev/null +++ b/arch/arm/plat-mxs/regs-icoll.h @@ -0,0 +1,293 @@ +/* + * Freescale ICOLL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H + +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) + +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) + +#define HW_ICOLL_STAT (0x00000070) + +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) + +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) + +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/plat-mxs/timer.c b/arch/arm/plat-mxs/timer.c new file mode 100644 index 000000000000..7d8f2477f4ba --- /dev/null +++ b/arch/arm/plat-mxs/timer.c @@ -0,0 +1,144 @@ +/* + * System timer for Freescale i.MXS + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/irq.h> +#include <linux/interrupt.h> + +#include <asm/mach/time.h> + +#include <mach/device.h> +#include <mach/regs-timrot.h> + +static struct mxs_sys_timer *online_timer; + +static irqreturn_t mxs_timer_handler(int irq, void *dev_id); + +static cycle_t mxs_get_cycles(struct clocksource *cs) +{ + return ~__raw_readl(online_timer->base + + HW_TIMROT_RUNNING_COUNTn(online_timer->id)); +} + +static int mxs_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + unsigned int match; + match = __raw_readl(online_timer->base + + HW_TIMROT_MATCH_COUNTn(online_timer->id)) - delta; + __raw_writel(match, online_timer->base + + HW_TIMROT_MATCH_COUNTn(online_timer->id)); + return (int)(match - + __raw_readl(online_timer->base + + HW_TIMROT_RUNNING_COUNTn(online_timer->id))) + > 0 ? -ETIME : 0; +} + +static void mxs_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ +} + +static struct clock_event_device mxs_clockevent = { + .name = "mxs tick timer ", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = mxs_set_next_event, + .set_mode = mxs_set_mode, + .rating = 200, +}; + +static struct clocksource mxs_clocksource = { + .name = "mxs clock source", + .rating = 250, + .read = mxs_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS +}; + +static struct irqaction mxs_timer_irq = { + .name = "i.MX/mxs Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxs_timer_handler, + .dev_id = &mxs_clockevent, +}; + +static int __init mxs_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + mxs_clocksource.mult = clocksource_hz2mult(c, mxs_clocksource.shift); + clocksource_register(&mxs_clocksource); + return 0; +} + +static int __init mxs_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + mxs_clockevent.mult = div_sc(c, NSEC_PER_SEC, mxs_clockevent.shift); + mxs_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mxs_clockevent); + mxs_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFFFFF0, + &mxs_clockevent); + mxs_clockevent.cpumask = cpumask_of(0); + + clockevents_register_device(&mxs_clockevent); + return 0; +} + +static irqreturn_t mxs_timer_handler(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + if (__raw_readl(online_timer->base + + HW_TIMROT_TIMCTRLn(online_timer->id)) & + BM_TIMROT_TIMCTRLn_IRQ) { + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + + HW_TIMROT_TIMCTRLn_CLR(online_timer->id)); + c->event_handler(c); + } + return IRQ_HANDLED; +} + +void mxs_timer_init(struct mxs_sys_timer *timer) +{ + if (!timer->base || !timer->clk || IS_ERR(timer->clk)) + return; + if (online_timer) + return; + online_timer = timer; + clk_enable(online_timer->clk); + __raw_writel(BF_TIMROT_TIMCTRLn_SELECT(online_timer->clk_sel) | + BM_TIMROT_TIMCTRLn_IRQ_EN | + BM_TIMROT_TIMCTRLn_MATCH_MODE, + online_timer->base + HW_TIMROT_TIMCTRLn(online_timer->id)); + mxs_clocksource_init(online_timer->clk); + mxs_clockevent_init(online_timer->clk); + setup_irq(online_timer->irq, &mxs_timer_irq); +} diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index febc40fd8456..fc1549fd585f 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1638,7 +1638,7 @@ mx35evb MACH_MX35EVB MX35EVB 1643 aml_m8050 MACH_AML_M8050 AML_M8050 1644 mx35_3ds MACH_MX35_3DS MX35_3DS 1645 mars MACH_MARS MARS 1646 -ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647 +neuros_osd2 MACH_NEUROS_OSD2 NEUROS_OSD2 1647 badger MACH_BADGER BADGER 1648 trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 @@ -1654,7 +1654,7 @@ vf10xx MACH_VF10XX VF10XX 1659 zoran43xx MACH_ZORAN43XX ZORAN43XX 1660 sonix926 MACH_SONIX926 SONIX926 1661 celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662 -cc9m2443 MACH_CC9M2443 CC9M2443 1663 +cc9m2443js MACH_CC9M2443JS CC9M2443JS 1663 tw5334 MACH_TW5334 TW5334 1664 omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665 nal_hlite MACH_NAL_HLITE NAL_HLITE 1666 @@ -1769,7 +1769,7 @@ mx31cicada MACH_MX31CICADA MX31CICADA 1777 mi424wr MACH_MI424WR MI424WR 1778 axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 -davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781 +davinci_da830_evm MACH_DAVINCI_DA830_EVM DAVINCI_DA830_EVM 1781 ep9302 MACH_EP9302 EP9302 1782 at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 cybook3 MACH_CYBOOK3 CYBOOK3 1784 @@ -1803,7 +1803,7 @@ ccw9p9215js MACH_CCW9P9215JS CCW9P9215JS 1811 rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812 sifmain MACH_SIFMAIN SIFMAIN 1813 sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814 -cc9m2443js MACH_CC9M2443JS CC9M2443JS 1815 +cc9m2443 MACH_CC9M2443 CC9M2443 1815 xaria300 MACH_XARIA300 XARIA300 1816 it9200 MACH_IT9200 IT9200 1817 rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818 @@ -1963,7 +1963,7 @@ ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971 arm11 MACH_ARM11 ARM11 1972 cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 -cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 +eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 cheflux MACH_CHEFLUX CHEFLUX 1976 eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 opcotec MACH_OPCOTEC OPCOTEC 1978 @@ -2250,14 +2250,14 @@ omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 darwin MACH_DARWIN DARWIN 2262 oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 rtsbc20 MACH_RTSBC20 RTSBC20 2264 -i780 MACH_I780 I780 2265 +sgh_i780 MACH_I780 I780 2265 gemini324 MACH_GEMINI324 GEMINI324 2266 oratislan MACH_ORATISLAN ORATISLAN 2267 oratisalog MACH_ORATISALOG ORATISALOG 2268 oratismadi MACH_ORATISMADI ORATISMADI 2269 oratisot16 MACH_ORATISOT16 ORATISOT16 2270 oratisdesk MACH_ORATISDESK ORATISDESK 2271 -v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272 +v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 sintexo MACH_SINTEXO SINTEXO 2273 cm3389 MACH_CM3389 CM3389 2274 omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 |