diff options
author | Mohit Kataria <mkataria@nvidia.com> | 2012-05-18 17:28:04 +0530 |
---|---|---|
committer | Varun Colbert <vcolbert@nvidia.com> | 2012-07-05 15:38:10 -0700 |
commit | e764753820cb723501692204d8d36c5103903a2c (patch) | |
tree | 0600fc0fe5941ce29756258d05461472a74bf95b /arch/arm | |
parent | 25033fb96283a8ba9018db9ec13b64ace8022101 (diff) |
ARM: Tegra: p1852: changed pinmux settings
Pinmux updated as per the latest pinmux sheet.
Bug 978870
Change-Id: I122439df3d043216f1c8c2c1a0a3c88e74d760ee
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/111573
(cherry picked from commit 4e65d7d21b5ac5b25e3563ce6a7eb50cf1d8128d)
Reviewed-on: http://git-master/r/103340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-pinmux.c | 122 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852-sdhci.c | 17 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board-p1852.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux-t3-tables.c | 12 |
4 files changed, 109 insertions, 52 deletions
diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c index 8d5edb066817..21f310b0ef16 100644 --- a/arch/arm/mach-tegra/board-p1852-pinmux.c +++ b/arch/arm/mach-tegra/board-p1852-pinmux.c @@ -170,6 +170,21 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ } +/* For LV(Low voltage) pad groups which has IO_RESET bit */ +#define LVPAD_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + + + static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { /* SDMMC1 pinmux */ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), @@ -191,14 +206,6 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW8, SDMMC2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW9, SDMMC2, PULL_UP, NORMAL, INPUT), - /* SDMMC3 pinmux */ - DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, PULL_UP, NORMAL, INPUT), - /* SDMMC4 pinmux */ DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, NORMAL, INPUT), @@ -210,6 +217,7 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GPIO_PBB5, POPSDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB6, POPSDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PBB7, POPSDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, POPSDMMC4, PULL_UP, NORMAL, INPUT), /* UART1 pinmux */ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), @@ -228,10 +236,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), /* UART5 pinmux */ - DEFAULT_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT), + LVPAD_PINMUX(SDMMC4_DAT0, UARTE, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT1, UARTE, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT2, UARTE, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT3, UARTE, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), /* I2C1 pinmux */ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), @@ -261,6 +269,12 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA6, SPI2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7, SPI2, NORMAL, NORMAL, INPUT), + /* SPI3 pinmux */ + DEFAULT_PINMUX(SDMMC3_CLK, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SPI3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SPI3, NORMAL, NORMAL, INPUT), + /* SPDIF pinmux */ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), @@ -277,10 +291,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), /* DAP3 */ - DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT), + LVPAD_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + LVPAD_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), /* NOR pinmux */ DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), @@ -299,8 +313,8 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_CS0_N, GMI, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, OUTPUT), @@ -376,6 +390,8 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, PULL_DOWN, NORMAL, INPUT), + VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), @@ -387,18 +403,37 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), /* pin config for gpios */ - DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_CS0_N, GMI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SAFE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_CS0_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_HSYNC, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CRT_VSYNC, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR2, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT), + LVPAD_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, RSVD0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), }; int __init p1852_pinmux_init(void) @@ -418,18 +453,37 @@ int __init p1852_pinmux_init(void) } static struct gpio_init_pin_info p1852_sku8_gpios[] = { - - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PT4, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PEE2, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PZ4, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD2, false, 1), - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD1, false, 1), - GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD0, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD0, true, 0), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW3, true, 0), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PK5, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX5, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX6, false, 1), GPIO_INIT_PIN_MODE(TEGRA_GPIO_PX7, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV0, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV6, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV7, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN6, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PW1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PB2, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC1, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PC6, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PZ2, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN5, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD3, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV2, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PV3, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD4, true, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC4, false, 0), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PA7, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PB4, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PD5, false, 1), + GPIO_INIT_PIN_MODE(TEGRA_GPIO_PN7, true, 0), }; int __init p1852_gpio_init(void) diff --git a/arch/arm/mach-tegra/board-p1852-sdhci.c b/arch/arm/mach-tegra/board-p1852-sdhci.c index c1aa066ae1b0..17fb451e27c5 100644 --- a/arch/arm/mach-tegra/board-p1852-sdhci.c +++ b/arch/arm/mach-tegra/board-p1852-sdhci.c @@ -3,7 +3,7 @@ * * Copyright (C) 2010 Google, Inc. * - * Copyright (C) 2012 NVIDIA Corporation + * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -35,9 +35,11 @@ #include "board-p1852.h" #include "devices.h" +#define P1852_SD1_CD TEGRA_GPIO_PV2 + static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = { - .cd_gpio = TEGRA_GPIO_PV2, - .wp_gpio = TEGRA_GPIO_PD3, + .cd_gpio = P1852_SD1_CD, + .wp_gpio = -1, .power_gpio = -1, .is_8bit = false, }; @@ -49,13 +51,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { .is_8bit = true, }; -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = TEGRA_GPIO_PV3, - .wp_gpio = TEGRA_GPIO_PD4, - .power_gpio = -1, - .is_8bit = false, -}; - static struct tegra_sdhci_platform_data tegra_sdhci_platform_data4 = { .cd_gpio = -1, .wp_gpio = -1, @@ -67,12 +62,10 @@ int __init p1852_sdhci_init(void) { tegra_sdhci_device1.dev.platform_data = &tegra_sdhci_platform_data1; tegra_sdhci_device2.dev.platform_data = &tegra_sdhci_platform_data2; - tegra_sdhci_device3.dev.platform_data = &tegra_sdhci_platform_data3; tegra_sdhci_device4.dev.platform_data = &tegra_sdhci_platform_data4; platform_device_register(&tegra_sdhci_device1); platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device3); platform_device_register(&tegra_sdhci_device4); return 0; diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index b589236f6b7c..a8ea75340997 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -305,6 +305,15 @@ static struct spi_board_info tegra_spi_devices[] __initdata = { }, { .modalias = "spidev", + .bus_num = 2, + .chip_select = 0, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", .bus_num = 3, .chip_select = 1, .mode = SPI_MODE_0, @@ -329,6 +338,7 @@ static void p1852_spi_init(void) tegra_spi_device2.name = "spi_slave_tegra"; platform_device_register(&tegra_spi_device1); platform_device_register(&tegra_spi_device2); + platform_device_register(&tegra_spi_device3); p852_register_spidev(); } diff --git a/arch/arm/mach-tegra/pinmux-t3-tables.c b/arch/arm/mach-tegra/pinmux-t3-tables.c index 90dbf757b909..09729a4cfbae 100644 --- a/arch/arm/mach-tegra/pinmux-t3-tables.c +++ b/arch/arm/mach-tegra/pinmux-t3-tables.c @@ -3,7 +3,7 @@ * * Common pinmux configurations for Tegra 3 SoCs * - * Copyright (C) 2010-2012 NVIDIA Corporation + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -320,7 +320,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(GPIO_PBB5, PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),\ PINGROUP(GPIO_PBB6, PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),\ PINGROUP(GPIO_PBB7, PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),\ - PINGROUP(GPIO_PCC2, PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),\ + PINGROUP(GPIO_PCC2, PCC2, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32ac),\ PINGROUP(JTAG_RTCK, PU7, SYS, RTCK, RSVD1, RSVD2, RSVD3, RTCK, INPUT, 0x32b0),\ PINGROUP(PWR_I2C_SCL, PZ6, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, I2CPWR, INPUT, 0x32b4),\ PINGROUP(PWR_I2C_SDA, PZ7, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, I2CPWR, INPUT, 0x32b8),\ @@ -377,11 +377,11 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(SPI1_MISO, PX7, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),\ PINGROUP(SPI2_CS1_N, PW2, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),\ PINGROUP(SPI2_CS2_N, PW3, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),\ - PINGROUP(SDMMC3_CLK, PA6, SDMMC3, UARTA, PWM2, SDMMC3, INVALID, SDMMC3, INPUT, 0x3390),\ + PINGROUP(SDMMC3_CLK, PA6, SDMMC3, UARTA, PWM2, SDMMC3, SPI3, SDMMC3, INPUT, 0x3390),\ PINGROUP(SDMMC3_CMD, PA7, SDMMC3, UARTA, PWM3, SDMMC3, INVALID, SDMMC3, INPUT, 0x3394),\ - PINGROUP(SDMMC3_DAT0, PB7, SDMMC3, RSVD0, RSVD1, SDMMC3, INVALID, SDMMC3, INPUT, 0x3398),\ - PINGROUP(SDMMC3_DAT1, PB6, SDMMC3, RSVD0, RSVD1, SDMMC3, INVALID, SDMMC3, INPUT, 0x339c),\ - PINGROUP(SDMMC3_DAT2, PB5, SDMMC3, RSVD0, PWM1, SDMMC3, INVALID, SDMMC3, INPUT, 0x33a0),\ + PINGROUP(SDMMC3_DAT0, PB7, SDMMC3, RSVD0, RSVD1, SDMMC3, SPI3, SDMMC3, INPUT, 0x3398),\ + PINGROUP(SDMMC3_DAT1, PB6, SDMMC3, RSVD0, RSVD1, SDMMC3, SPI3, SDMMC3, INPUT, 0x339c),\ + PINGROUP(SDMMC3_DAT2, PB5, SDMMC3, RSVD0, PWM1, SDMMC3, SPI3, SDMMC3, INPUT, 0x33a0),\ PINGROUP(SDMMC3_DAT3, PB4, SDMMC3, RSVD0, PWM0, SDMMC3, INVALID, SDMMC3, INPUT, 0x33a4),\ PINGROUP(SDMMC3_DAT4, PD1, SDMMC3, PWM1, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33a8),\ PINGROUP(SDMMC3_DAT5, PD0, SDMMC3, PWM0, INVALID, SDMMC3, INVALID, SDMMC3, INPUT, 0x33ac),\ |