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authorFugang Duan <b38611@freescale.com>2014-12-08 18:40:02 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-09-17 09:20:15 -0500
commitcc54d2a8fe8de412dc1a04a7c7022fe1183a3c2e (patch)
tree384a4774487ed92514d41c7075fab061ca4a5c7c /arch/arm
parentf31747df67ff04817b4dfbbdba8575baccb0df20 (diff)
ENGR00322839 ARM: dts: imx6sx: enet RGMII TXCLK output drive strength is weak
The current enet RGMII TXCLK rise/fall time which could be observed(~0.85ns) is longer than requirement (<=0.75ns). The current setting, SPEED/DSE/SRE=10/110/1 is used, and then it needs to increase DSE to 111 "37 Ohm @ 3.3V, 21 Ohm@1.8V, 34 Ohm for DDR". After the change RGMII TXCLK match the spec requirement. Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 5bca5fb2af29..e406d534524a 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -641,7 +641,7 @@
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
- MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1