diff options
| author | Seema Khowala <seemaj@nvidia.com> | 2013-08-06 16:26:14 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:44:51 -0700 |
| commit | 46f7d0f7697b3e47760c35c08d538c79cbe77492 (patch) | |
| tree | 79156f6d167b02cb9df29d469181e85298409486 /arch/arm | |
| parent | bc86e01fab8372a31eca7389f4b57e80338b839d (diff) | |
arm: tegra: ardbeg: Support E1792
E1792 is same as Sheild E1780 SKU1000 except
the Memory.E1792 has LPDDR3(EDFA164A2MA-JD-F,
LPDDR3 x32, 933Mhz, 16Gb) instead.
Default DDR voltage for E1733 and E1735 pmu
is 1.35V but lpddr3 supports 1.2V
Bug 1339736
Change-Id: Ie1e23e3512876940349ee6c4c915c890b5ebfdad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/263470
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-power.c | 16 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra-board-id.h | 1 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-power.c b/arch/arm/mach-tegra/board-ardbeg-power.c index 10829af6ec10..6ccdfea3035f 100644 --- a/arch/arm/mach-tegra/board-ardbeg-power.c +++ b/arch/arm/mach-tegra/board-ardbeg-power.c @@ -362,7 +362,7 @@ int __init ardbeg_as3722_regulator_init(void) { void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); u32 pmc_ctrl; - + struct board_info board_info; /* AS3722: Normal state of INT request line is LOW. * configure the power management controller to trigger PMU @@ -386,6 +386,13 @@ int __init ardbeg_as3722_regulator_init(void) as3722_sd1_reg_pdata.oc_trip_thres_perphase = 2500; as3722_sd1_reg_pdata.oc_alarm_thres_perphase = 0; + tegra_get_board_info(&board_info); + if (board_info.board_id == BOARD_E1792) { + /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/ + as3722_sd2_reg_idata.constraints.min_uV = 1200000; + as3722_sd2_reg_idata.constraints.max_uV = 1200000; + } + pr_info("%s: i2c_register_board_info\n", __func__); i2c_register_board_info(4, as3722_regulators, ARRAY_SIZE(as3722_regulators)); @@ -600,6 +607,7 @@ int __init ardbeg_tps65913_regulator_init(void) void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); u32 pmc_ctrl; int i; + struct board_info board_info; /* TPS65913: Normal state of INT request line is LOW. * configure the power management controller to trigger PMU @@ -621,6 +629,12 @@ int __init ardbeg_tps65913_regulator_init(void) /* Set vdd_gpu init uV to 1V */ reg_idata_ti913_smps123.constraints.init_uV = 900000; + tegra_get_board_info(&board_info); + if (board_info.board_id == BOARD_E1792) { + /*Default DDR voltage is 1.35V but lpddr3 supports 1.2V*/ + reg_idata_ti913_smps7.constraints.max_uV = 1200000; + } + i2c_register_board_info(4, palma_ti913_device, ARRAY_SIZE(palma_ti913_device)); return 0; diff --git a/arch/arm/mach-tegra/tegra-board-id.h b/arch/arm/mach-tegra/tegra-board-id.h index 3e65f3de3b80..e22904745add 100644 --- a/arch/arm/mach-tegra/tegra-board-id.h +++ b/arch/arm/mach-tegra/tegra-board-id.h @@ -45,6 +45,7 @@ #define BOARD_P2560 0x0A00 #define BOARD_E1780 0x06F4 #define BOARD_E1781 0x06F5 +#define BOARD_E1792 0x0700 #define BOARD_PM358 0x0166 #define BOARD_PM359 0x0167 #define BOARD_PM363 0x016B |