tegra: apalis_t30: initial Toradex Apalis T30 L4T support

Tested on early prototype Apalis T30 V1.0a module.

Known issues:

- ADC not integrated yet.

- HDA not integrated yet.

- CEC not integrated yet.

- IrDA not integrated yet.

- Keys not integrated yet therefore no way to wake from suspend.

- 8-bit MMC1 slot card detection interrupt not working despite
detection GPIO successfully being tested with GPIOConfig.
Note: even 8-bit cards work fine if already plugged-in during boot.

- PCIe limited to internal Gigabit Ethernet chip for now due to our
proprietary way of resetting other ports which requires further
integration into NVIDIA's driver.

13 files changed, 5584 insertions, 7 deletions

diff --git a/arch/arm/configs/apalis_t30_defconfig b/arch/arm/configs/apalis_t30_defconfig
new file mode 100644
index 000000000000..ae061bfed3b4
--- /dev/null
+++ b/arch/arm/configs/apalis_t30_defconfig
@@ -0,0 +1,354 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PCI_QUIRKS is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_TEGRA_PCI=y
+CONFIG_MACH_APALIS_T30=y
+CONFIG_TEGRA_PWM=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y
+CONFIG_USB_HOTPLUG=y
+CONFIG_TEGRA_DYNAMIC_PWRDET=y
+CONFIG_TEGRA_PLLM_RESTRICTED=y
+CONFIG_TEGRA_PREINIT_CLOCKS=y
+CONFIG_ARM_ERRATA_742230=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_752520=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEASPM_POWERSAVE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_SUSPEND_TIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_U32=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+CONFIG_NET_ACT_MIRRED=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251X=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_BLUESLEEP=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_MISC_DEVICES=y
+CONFIG_UID_STAT=y
+CONFIG_TEGRA_CRYPTO_DEV=y
+# CONFIG_INV_SENSORS is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_TEGRA=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_NETDEV_1000=y
+CONFIG_IGB=y
+# CONFIG_NETDEV_10000 is not set
+# Hack to force WIRELESS_EXT required to build Redpine Signals LiteFi driver
+CONFIG_USB_ZD1201=m
+CONFIG_RT2X00=y
+CONFIG_RT2800USB=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_PPP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYRESET=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=9
+CONFIG_SERIAL_8250_RUNTIME_UARTS=9
+CONFIG_SERIAL_TEGRA=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_TEGRA=y
+CONFIG_SPI=y
+CONFIG_SPI_TEGRA=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_LM95245=y
+CONFIG_SENSORS_TEGRA_TSENSOR=y
+CONFIG_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_TEGRA_WATCHDOG=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_TPS6591X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS6591X=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_TEGRA_AVP is not set
+# CONFIG_TEGRA_MEDIASERVER is not set
+CONFIG_TEGRA_NVAVP=y
+# CONFIG_TEGRA_DTV is not set
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_TEGRA_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_PCI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_COLIBRI_T30=y
+CONFIG_HIDRAW=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_WDM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_TEGRA=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BKOPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_SWITCH=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_TPS6591x=y
+CONFIG_STAGING=y
+CONFIG_IIO=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=m
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_TWOFISH=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_SE=y
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index cf9668ca1f6b..915b1abf7b00 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -169,6 +169,13 @@ config MACH_WHISTLER
        help
          Support for NVIDIA Whistler development platform
 
+config MACH_APALIS_T30
+       bool "Toradex Apalis T30 module"
+       depends on ARCH_TEGRA_3x_SOC
+       help
+         Support for Toradex Apalis T30 module on Apalis evaluation carrier
+         board
+
 config MACH_ARUBA
        bool "Aruba board"
        depends on ARCH_TEGRA_3x_SOC
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 9a476876374a..9e6918a3f986 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -183,6 +183,12 @@ obj-${CONFIG_MACH_CARDHU}               += board-cardhu-sensors.o
 obj-${CONFIG_MACH_CARDHU}               += board-cardhu-memory.o
 obj-${CONFIG_MACH_CARDHU}               += board-cardhu-powermon.o
 
+obj-${CONFIG_MACH_APALIS_T30}           += board-apalis_t30.o
+obj-${CONFIG_MACH_APALIS_T30}           += board-apalis_t30-panel.o
+obj-${CONFIG_MACH_APALIS_T30}           += board-apalis_t30-pinmux.o
+obj-${CONFIG_MACH_APALIS_T30}           += board-apalis_t30-power.o
+obj-${CONFIG_MACH_APALIS_T30}           += board-apalis_t30-memory.o
+
 obj-${CONFIG_MACH_COLIBRI_T30}          += board-colibri_t30.o
 obj-${CONFIG_MACH_COLIBRI_T30}          += board-colibri_t30-panel.o
 obj-${CONFIG_MACH_COLIBRI_T30}          += board-colibri_t30-pinmux.o
diff --git a/arch/arm/mach-tegra/board-apalis_t30-memory.c b/arch/arm/mach-tegra/board-apalis_t30-memory.c
new file mode 100644
index 000000000000..ee3d3858e285
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30-memory.c
@@ -0,0 +1,2091 @@
+/*
+ * Copyright (C) 2013 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "board.h"
+#include "board-apalis_t30.h"
+#include "tegra3_emc.h"
+#include "fuse.h"
+
+#if 0
+static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
+	{
+		0x32,       /* Rev 3.2 */
+		25500,      /* SDRAM frequency */
+		{
+			0x00000001, /* EMC_RC */
+			0x00000003, /* EMC_RFC */
+			0x00000000, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x000000bd, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000005, /* EMC_TXSR */
+			0x00000005, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000001, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x000000c3, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00030003, /* MC_EMEM_ARB_CFG */
+			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x74430303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		51000,      /* SDRAM frequency */
+		{
+			0x00000002, /* EMC_RC */
+			0x00000008, /* EMC_RFC */
+			0x00000001, /* EMC_RAS */
+			0x00000000, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000000, /* EMC_RD_RCD */
+			0x00000000, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000181, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000009, /* EMC_TXSR */
+			0x00000009, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000002, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000018e, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00010003, /* MC_EMEM_ARB_CFG */
+			0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+			0x73430303, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		102000,     /* SDRAM frequency */
+		{
+			0x00000004, /* EMC_RC */
+			0x00000010, /* EMC_RFC */
+			0x00000003, /* EMC_RAS */
+			0x00000001, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000001, /* EMC_RD_RCD */
+			0x00000001, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000007, /* EMC_QSAFE */
+			0x0000000c, /* EMC_RDV */
+			0x00000303, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000012, /* EMC_TXSR */
+			0x00000012, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000004, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x0000031c, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00006288, /* EMC_FBIO_CFG5 */
+			0x007800a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000003, /* MC_EMEM_ARB_CFG */
+			0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+			0x72830504, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xd8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		204000,     /* SDRAM frequency */
+		{
+			0x00000009, /* EMC_RC */
+			0x00000020, /* EMC_RFC */
+			0x00000007, /* EMC_RAS */
+			0x00000002, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x0000000a, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x0000000b, /* EMC_W2P */
+			0x00000002, /* EMC_RD_RCD */
+			0x00000002, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000009, /* EMC_QSAFE */
+			0x0000000b, /* EMC_RDV */
+			0x00000607, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000002, /* EMC_PDEX2WR */
+			0x00000002, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000023, /* EMC_TXSR */
+			0x00000023, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x00000007, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000638, /* EMC_TREFBW */
+			0x00000006, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00004288, /* EMC_FBIO_CFG5 */
+			0x004400a4, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00080000, /* EMC_DLL_XFORM_DQS0 */
+			0x00080000, /* EMC_DLL_XFORM_DQS1 */
+			0x00080000, /* EMC_DLL_XFORM_DQS2 */
+			0x00080000, /* EMC_DLL_XFORM_DQS3 */
+			0x00080000, /* EMC_DLL_XFORM_DQS4 */
+			0x00080000, /* EMC_DLL_XFORM_DQS5 */
+			0x00080000, /* EMC_DLL_XFORM_DQS6 */
+			0x00080000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00080000, /* EMC_DLL_XFORM_DQ0 */
+			0x00080000, /* EMC_DLL_XFORM_DQ1 */
+			0x00080000, /* EMC_DLL_XFORM_DQ2 */
+			0x00080000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f108, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000000, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x000c000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000006, /* MC_EMEM_ARB_CFG */
+			0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0505, /* MC_EMEM_ARB_DA_COVERS */
+			0x72440a06, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80001221, /* Mode Register 0 */
+		0x80100003, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000001, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		375000,     /* SDRAM frequency */
+		{
+			0x00000011, /* EMC_RC */
+			0x0000003a, /* EMC_RFC */
+			0x0000000c, /* EMC_RAS */
+			0x00000004, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000008, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000a, /* EMC_W2P */
+			0x00000004, /* EMC_RD_RCD */
+			0x00000004, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000004, /* EMC_WDV */
+			0x00000006, /* EMC_QUSE */
+			0x00000004, /* EMC_QRST */
+			0x00000008, /* EMC_QSAFE */
+			0x0000000d, /* EMC_RDV */
+			0x00000b2d, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000008, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000007, /* EMC_AR2PDEN */
+			0x0000000f, /* EMC_RW2PDEN */
+			0x00000040, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000009, /* EMC_TCKE */
+			0x0000000c, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000b6d, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x00200084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0003c000, /* EMC_DLL_XFORM_DQS0 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS1 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS2 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS3 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS4 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS5 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS6 */
+			0x0003c000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00040000, /* EMC_DLL_XFORM_DQ0 */
+			0x00040000, /* EMC_DLL_XFORM_DQ1 */
+			0x00040000, /* EMC_DLL_XFORM_DQ2 */
+			0x00040000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0184000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000b, /* MC_EMEM_ARB_CFG */
+			0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000009, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
+			0x75c6110a, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x58000000, /* EMC_FBIO_SPARE */
+			0xff00ff88, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000521, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200000, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		400000,     /* SDRAM frequency */
+		{
+			0x00000012, /* EMC_RC */
+			0x00000040, /* EMC_RFC */
+			0x0000000d, /* EMC_RAS */
+			0x00000004, /* EMC_RP */
+			0x00000002, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000c, /* EMC_W2P */
+			0x00000004, /* EMC_RD_RCD */
+			0x00000004, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_QRST */
+			0x00000008, /* EMC_QSAFE */
+			0x0000000e, /* EMC_RDV */
+			0x00000c2e, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000008, /* EMC_PDEX2WR */
+			0x00000008, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000008, /* EMC_AR2PDEN */
+			0x00000011, /* EMC_RW2PDEN */
+			0x00000046, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x0000000a, /* EMC_TCKE */
+			0x0000000d, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000c6f, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x001c0084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00034000, /* EMC_DLL_XFORM_DQS0 */
+			0x00034000, /* EMC_DLL_XFORM_DQS1 */
+			0x00034000, /* EMC_DLL_XFORM_DQS2 */
+			0x00034000, /* EMC_DLL_XFORM_DQS3 */
+			0x00034000, /* EMC_DLL_XFORM_DQS4 */
+			0x00034000, /* EMC_DLL_XFORM_DQS5 */
+			0x00034000, /* EMC_DLL_XFORM_DQS6 */
+			0x00034000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00040000, /* EMC_DLL_XFORM_DQ0 */
+			0x00040000, /* EMC_DLL_XFORM_DQ1 */
+			0x00040000, /* EMC_DLL_XFORM_DQ2 */
+			0x00040000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x017f000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000c, /* MC_EMEM_ARB_CFG */
+			0xc000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
+			0x7547130b, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x58000000, /* EMC_FBIO_SPARE */
+			0xff00ff88, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000731, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		450000,     /* SDRAM frequency */
+		{
+			0x00000014, /* EMC_RC */
+			0x00000046, /* EMC_RFC */
+			0x0000000e, /* EMC_RAS */
+			0x00000005, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000c, /* EMC_W2P */
+			0x00000005, /* EMC_RD_RCD */
+			0x00000005, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000007, /* EMC_QUSE */
+			0x00000005, /* EMC_QRST */
+			0x0000000a, /* EMC_QSAFE */
+			0x0000000e, /* EMC_RDV */
+			0x00000d76, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000001, /* EMC_PDEX2WR */
+			0x00000009, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000009, /* EMC_AR2PDEN */
+			0x00000011, /* EMC_RW2PDEN */
+			0x0000004d, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000004, /* EMC_TCKE */
+			0x0000000e, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000004, /* EMC_TCLKSTABLE */
+			0x00000005, /* EMC_TCLKSTOP */
+			0x00000db6, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x00180084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00022000, /* EMC_DLL_XFORM_DQS0 */
+			0x00022000, /* EMC_DLL_XFORM_DQS1 */
+			0x00022000, /* EMC_DLL_XFORM_DQS2 */
+			0x00022000, /* EMC_DLL_XFORM_DQS3 */
+			0x00022000, /* EMC_DLL_XFORM_DQS4 */
+			0x00022000, /* EMC_DLL_XFORM_DQS5 */
+			0x00022000, /* EMC_DLL_XFORM_DQS6 */
+			0x00022000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00030000, /* EMC_DLL_XFORM_DQ0 */
+			0x00030000, /* EMC_DLL_XFORM_DQ1 */
+			0x00030000, /* EMC_DLL_XFORM_DQ2 */
+			0x00030000, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0178000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000d, /* MC_EMEM_ARB_CFG */
+			0xc0000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
+			0x70a7150c, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff8b, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000731, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		533000,     /* SDRAM frequency */
+		{
+			0x00000018, /* EMC_RC */
+			0x00000054, /* EMC_RFC */
+			0x00000011, /* EMC_RAS */
+			0x00000006, /* EMC_RP */
+			0x00000003, /* EMC_R2W */
+			0x00000009, /* EMC_W2R */
+			0x00000002, /* EMC_R2P */
+			0x0000000d, /* EMC_W2P */
+			0x00000006, /* EMC_RD_RCD */
+			0x00000006, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000005, /* EMC_WDV */
+			0x00000008, /* EMC_QUSE */
+			0x00000006, /* EMC_QRST */
+			0x00000008, /* EMC_QSAFE */
+			0x00000010, /* EMC_RDV */
+			0x00000ffd, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x0000000b, /* EMC_PDEX2WR */
+			0x0000000b, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000a, /* EMC_AR2PDEN */
+			0x00000012, /* EMC_RW2PDEN */
+			0x0000005b, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x0000000d, /* EMC_TCKE */
+			0x00000010, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000005, /* EMC_TCLKSTABLE */
+			0x00000006, /* EMC_TCLKSTOP */
+			0x0000103e, /* EMC_TREFBW */
+			0x00000000, /* EMC_QUSE_EXTRA */
+			0x00000006, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00007088, /* EMC_FBIO_CFG5 */
+			0x00120084, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00010000, /* EMC_DLL_XFORM_DQS0 */
+			0x00010000, /* EMC_DLL_XFORM_DQS1 */
+			0x00010000, /* EMC_DLL_XFORM_DQS2 */
+			0x00010000, /* EMC_DLL_XFORM_DQS3 */
+			0x00010000, /* EMC_DLL_XFORM_DQS4 */
+			0x00010000, /* EMC_DLL_XFORM_DQS5 */
+			0x00010000, /* EMC_DLL_XFORM_DQS6 */
+			0x00010000, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00020000, /* EMC_DLL_XFORM_DQ0 */
+			0x00020000, /* EMC_DLL_XFORM_DQ1 */
+			0x00020000, /* EMC_DLL_XFORM_DQ2 */
+			0x00020000, /* EMC_DLL_XFORM_DQ3 */
+			0x000006a0, /* EMC_XM2CMDPADCTRL */
+			0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77ffc084, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x05057404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+			0x08000168, /* EMC_XM2QUSEPADCTRL */
+			0x08000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00000000, /* EMC_ZCAL_INTERVAL */
+			0x00000040, /* EMC_ZCAL_WAIT_CNT */
+			0x01ab000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000000f, /* MC_EMEM_ARB_CFG */
+			0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+			0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+			0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
+			0x7028180e, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0x00000000, /* EMC_FBIO_SPARE */
+			0xff00ff00, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000000, /* EMC_CFG.PERIODIC_QRST */
+		0x80000941, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200008, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		667000,     /* SDRAM frequency */
+		{
+			0x0000001f, /* EMC_RC */
+			0x00000069, /* EMC_RFC */
+			0x00000016, /* EMC_RAS */
+			0x00000008, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000c, /* EMC_W2R */
+			0x00000003, /* EMC_R2P */
+			0x00000011, /* EMC_W2P */
+			0x00000008, /* EMC_RD_RCD */
+			0x00000008, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x00001412, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x0000000e, /* EMC_PDEX2WR */
+			0x0000000e, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000c, /* EMC_AR2PDEN */
+			0x00000016, /* EMC_RW2PDEN */
+			0x00000072, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000010, /* EMC_TCKE */
+			0x00000015, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000006, /* EMC_TCLKSTABLE */
+			0x00000007, /* EMC_TCLKSTOP */
+			0x00001453, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0x40070191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x00000008, /* EMC_DLL_XFORM_DQ0 */
+			0x00000008, /* EMC_DLL_XFORM_DQ1 */
+			0x00000008, /* EMC_DLL_XFORM_DQ2 */
+			0x00000008, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x00000000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f508, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x01d6000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000014, /* MC_EMEM_ARB_CFG */
+			0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000010, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00140c10, /* MC_EMEM_ARB_DA_COVERS */
+			0x734a1f11, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xf8000000, /* EMC_FBIO_SPARE */
+			0xff00ff01, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000b71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200018, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		750000,     /* SDRAM frequency */
+		{
+			0x00000025, /* EMC_RC */
+			0x0000007e, /* EMC_RFC */
+			0x0000001a, /* EMC_RAS */
+			0x00000009, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x00000009, /* EMC_RD_RCD */
+			0x00000009, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x0000169a, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000012, /* EMC_PDEX2WR */
+			0x00000012, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000f, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x00000088, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000014, /* EMC_TCKE */
+			0x00000018, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000007, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001860, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf0080191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x00000008, /* EMC_DLL_XFORM_DQS0 */
+			0x00000008, /* EMC_DLL_XFORM_DQS1 */
+			0x00000008, /* EMC_DLL_XFORM_DQS2 */
+			0x00000008, /* EMC_DLL_XFORM_DQS3 */
+			0x00000008, /* EMC_DLL_XFORM_DQS4 */
+			0x00000008, /* EMC_DLL_XFORM_DQS5 */
+			0x00000008, /* EMC_DLL_XFORM_DQS6 */
+			0x00000008, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0180000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000016, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
+			0x72ac2414, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xf8000000, /* EMC_FBIO_SPARE */
+			0xff00ff49, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000d71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200018, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		800000,     /* SDRAM frequency */
+		{
+			0x00000025, /* EMC_RC */
+			0x0000007e, /* EMC_RFC */
+			0x0000001a, /* EMC_RAS */
+			0x00000009, /* EMC_RP */
+			0x00000004, /* EMC_R2W */
+			0x0000000d, /* EMC_W2R */
+			0x00000004, /* EMC_R2P */
+			0x00000013, /* EMC_W2P */
+			0x00000009, /* EMC_RD_RCD */
+			0x00000009, /* EMC_WR_RCD */
+			0x00000003, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000007, /* EMC_WDV */
+			0x0000000b, /* EMC_QUSE */
+			0x00000009, /* EMC_QRST */
+			0x0000000c, /* EMC_QSAFE */
+			0x00000011, /* EMC_RDV */
+			0x00001820, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000012, /* EMC_PDEX2WR */
+			0x00000012, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x0000000f, /* EMC_AR2PDEN */
+			0x00000018, /* EMC_RW2PDEN */
+			0x00000088, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000014, /* EMC_TCKE */
+			0x00000018, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000007, /* EMC_TCLKSTABLE */
+			0x00000008, /* EMC_TCLKSTOP */
+			0x00001860, /* EMC_TREFBW */
+			0x0000000c, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf0070191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0000800a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
+			0x0180000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
+			0x00000018, /* MC_EMEM_ARB_CFG */
+			0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+			0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+			0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
+			0x72ac2414, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xf8000000, /* EMC_FBIO_SPARE */
+			0xff00ff49, /* EMC_CFG_RSV */
+		},
+		0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000d71, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200018, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		900000,     /* SDRAM frequency */
+		{
+			0x0000002a, /* EMC_RC */
+			0x0000008e, /* EMC_RFC */
+			0x0000001e, /* EMC_RAS */
+			0x0000000b, /* EMC_RP */
+			0x00000006, /* EMC_R2W */
+			0x0000000f, /* EMC_W2R */
+			0x00000005, /* EMC_R2P */
+			0x00000016, /* EMC_W2P */
+			0x0000000b, /* EMC_RD_RCD */
+			0x0000000b, /* EMC_WR_RCD */
+			0x00000004, /* EMC_RRD */
+			0x00000001, /* EMC_REXT */
+			0x00000000, /* EMC_WEXT */
+			0x00000008, /* EMC_WDV */
+			0x0000000d, /* EMC_QUSE */
+			0x0000000b, /* EMC_QRST */
+			0x0000000b, /* EMC_QSAFE */
+			0x00000014, /* EMC_RDV */
+			0x00001b2c, /* EMC_REFRESH */
+			0x00000000, /* EMC_BURST_REFRESH_NUM */
+			0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000004, /* EMC_PDEX2WR */
+			0x00000014, /* EMC_PDEX2RD */
+			0x00000001, /* EMC_PCHG2PDEN */
+			0x00000000, /* EMC_ACT2PDEN */
+			0x00000011, /* EMC_AR2PDEN */
+			0x0000001b, /* EMC_RW2PDEN */
+			0x00000099, /* EMC_TXSR */
+			0x00000200, /* EMC_TXSRDLL */
+			0x00000006, /* EMC_TCKE */
+			0x0000001b, /* EMC_TFAW */
+			0x00000000, /* EMC_TRPAB */
+			0x00000008, /* EMC_TCLKSTABLE */
+			0x00000009, /* EMC_TCLKSTOP */
+			0x00001b6c, /* EMC_TREFBW */
+			0x0000000e, /* EMC_QUSE_EXTRA */
+			0x00000004, /* EMC_FBIO_CFG6 */
+			0x00000000, /* EMC_ODT_WRITE */
+			0x00000000, /* EMC_ODT_READ */
+			0x00005088, /* EMC_FBIO_CFG5 */
+			0xf0040191, /* EMC_CFG_DIG_DLL */
+			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+			0x0000800a, /* EMC_DLL_XFORM_DQS0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+			0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE0 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE1 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE2 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE3 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE4 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE5 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE6 */
+			0x0001c000, /* EMC_DLL_XFORM_QUSE7 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+			0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+			0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+			0x000002a0, /* EMC_XM2CMDPADCTRL */
+			0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+			0x22220000, /* EMC_XM2DQPADCTRL2 */
+			0x77fff884, /* EMC_XM2CLKPADCTRL */
+			0x01f1f501, /* EMC_XM2COMPPADCTRL */
+			0x07077404, /* EMC_XM2VTTGENPADCTRL */
+			0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+			0x080001e8, /* EMC_XM2QUSEPADCTRL */
+			0x07000021, /* EMC_XM2DQSPADCTRL3 */
+			0x00000802, /* EMC_CTT_TERM_CTRL */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000120, /* EMC_ZCAL_WAIT_CNT */
+			0x0128000c, /* EMC_MRS_WAIT_CNT */
+			0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+			0x00000000, /* EMC_CTT */
+			0x00000000, /* EMC_CTT_DURATION */
+			0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000001b, /* MC_EMEM_ARB_CFG */
+			0xc00000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+			0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+			0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
+			0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+			0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+			0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+			0x09050202, /* MC_EMEM_ARB_DA_TURNS */
+			0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
+			0x714e2917, /* MC_EMEM_ARB_MISC0 */
+			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+			0xe8000000, /* EMC_FBIO_SPARE */
+			0xff00ff4b, /* EMC_CFG_RSV */
+		},
+		0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
+		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+		0x00000001, /* EMC_CFG.PERIODIC_QRST */
+		0x80000f15, /* Mode Register 0 */
+		0x80100002, /* Mode Register 1 */
+		0x80200020, /* Mode Register 2 */
+		0x00000000, /* EMC_CFG.DYN_SELF_REF */
+	},
+};
+#endif
+
+static const struct tegra_emc_table apalis_t30_emc_tables_mt41k256m16re_15e[] = {
+//25.5, 51, 102
+	{
+		0x32,       /* Rev 3.2 */
+//204 MHz crashes
+		200000,     /* SDRAM frequency [kHz] */
+		{
+			0x0000000a,  /* EmcRc */
+			0x00000033,  /* EmcRfc */
+			0x00000007,  /* EmcRas */
+			0x00000002,  /* EmcRp */
+			0x00000003,  /* EmcR2w */
+			0x00000009,  /* EmcW2r */
+			0x00000005,  /* EmcR2p */
+			0x0000000a,  /* EmcW2p */
+			0x00000002,  /* EmcRdRcd */
+			0x00000002,  /* EmcWrRcd */
+			0x00000003,  /* EmcRrd */
+			0x00000001,  /* EmcRext */
+			0x00000000,  /* EmcWext */
+			0x00000004,  /* EmcWdv */
+			0x00000005,  /* EmcQUse */
+			0x00000004,  /* EmcQRst */
+			0x00000009,  /* EmcQSafe */
+			0x0000000b,  /* EmcRdv */
+			0x000005e9,  /* EmcRefresh */
+			0x00000000,  /* EmcBurstRefreshNum */
+			0x0000017a,  /* EmcPreRefreshReqCnt */
+			0x00000002,  /* EmcPdEx2Wr */
+			0x00000002,  /* EmcPdEx2Rd */
+			0x00000001,  /* EmcPChg2Pden */
+			0x00000000,  /* EmcAct2Pden */
+			0x00000007,  /* EmcAr2Pden */
+			0x0000000e,  /* EmcRw2Pden */
+			0x00000036,  /* EmcTxsr */
+			0x00000134,  /* EmcTxsrDll */
+			0x00000004,  /* EmcTcke */
+			0x0000000a,  /* EmcTfaw */
+			0x00000000,  /* EmcTrpab */
+			0x00000004,  /* EmcTClkStable */
+			0x00000005,  /* EmcTClkStop */
+			0x00000618,  /* EmcTRefBw */
+			0x00000006,  /* EmcQUseExtra */
+			0x00000004,  /* EmcFbioCfg6 */
+			0x00000000,  /* EmcOdtWrite */
+			0x00000000,  /* EmcOdtRead */
+			0x00004288,  /* EmcFbioCfg5 */
+			0x004600a4,  /* EmcCfgDigDll */
+			0x00008000,  /* EmcCfgDigDllPeriod */
+			0x00080000,  /* EmcDllXformDqs0 */
+			0x00080000,  /* EmcDllXformDqs1 */
+			0x00080000,  /* EmcDllXformDqs2 */
+			0x00080000,  /* EmcDllXformDqs3 */
+			0x00080000,  /* EmcDllXformDqs4 */
+			0x00080000,  /* EmcDllXformDqs5 */
+			0x00080000,  /* EmcDllXformDqs6 */
+			0x00080000,  /* EmcDllXformDqs7 */
+			0x00000000,  /* EmcDllXformQUse0 */
+			0x00000000,  /* EmcDllXformQUse1 */
+			0x00000000,  /* EmcDllXformQUse2 */
+			0x00000000,  /* EmcDllXformQUse3 */
+			0x00000000,  /* EmcDllXformQUse4 */
+			0x00000000,  /* EmcDllXformQUse5 */
+			0x00000000,  /* EmcDllXformQUse6 */
+			0x00000000,  /* EmcDllXformQUse7 */
+			0x00000000,  /* EmcDliTrimTxDqs0 */
+			0x00000000,  /* EmcDliTrimTxDqs1 */
+			0x00000000,  /* EmcDliTrimTxDqs2 */
+			0x00000000,  /* EmcDliTrimTxDqs3 */
+			0x00000000,  /* EmcDliTrimTxDqs4 */
+			0x00000000,  /* EmcDliTrimTxDqs5 */
+			0x00000000,  /* EmcDliTrimTxDqs6 */
+			0x00000000,  /* EmcDliTrimTxDqs7 */
+			0x00080000,  /* EmcDllXformDq0 */
+			0x00080000,  /* EmcDllXformDq1 */
+			0x00080000,  /* EmcDllXformDq2 */
+			0x00080000,  /* EmcDllXformDq3 */
+			0x000002a0,  /* EmcXm2CmdPadCtrl */
+			0x0800211c,  /* EmcXm2DqsPadCtrl2 */
+			0x00000000,  /* EmcXm2DqPadCtrl2 */
+			0x77fff884,  /* EmcXm2ClkPadCtrl */
+			0x01f1f108,  /* EmcXm2CompPadCtrl */
+			0x05057404,  /* EmcXm2VttGenPadCtrl */
+			0x54000007,  /* EmcXm2VttGenPadCtrl2 */
+			0x08000168,  /* EmcXm2QUsePadCtrl */
+			0x08000000,  /* EmcXm2DqsPadCtrl3 */
+			0x00000802,  /* EmcCttTermCtrl */
+			0x00020000,  /* EmcZcalInterval */
+			0x00000040,  /* EmcZcalWaitCnt */
+			0x000c000c,  /* EmcMrsWaitCnt */
+			0x001fffff,  /* EmcAutoCalInterval */
+			0x00000000,  /* EmcCtt */
+			0x00000000,  /* EmcCttDuration */
+			0x80000ce6,  /* EmcDynSelfRefControl */
+			0x00000003,  /* McEmemArbCfg */
+			0xc0000024,  /* McEmemArbOutstandingReq */
+			0x00000001,  /* McEmemArbTimingRcd */
+			0x00000001,  /* McEmemArbTimingRp */
+			0x00000005,  /* McEmemArbTimingRc */
+			0x00000002,  /* McEmemArbTimingRas */
+			0x00000004,  /* McEmemArbTimingFaw */
+			0x00000001,  /* McEmemArbTimingRrd */
+			0x00000003,  /* McEmemArbTimingRap2Pre */
+			0x00000007,  /* McEmemArbTimingWap2Pre */
+			0x00000002,  /* McEmemArbTimingR2R */
+			0x00000001,  /* McEmemArbTimingW2W */
+			0x00000003,  /* McEmemArbTimingR2W */
+			0x00000006,  /* McEmemArbTimingW2R */
+			0x06030102,  /* McEmemArbDaTurns */
+			0x00090505,  /* McEmemArbDaCovers */
+			0x76a30906,  /* McEmemArbMisc0 */
+			0x001f0000,  /* McEmemArbRing1Throttle */
+			0xe8000000,  /* EmcFbioSpare */
+			0xff00ff00,  /* EmcCfgRsv */
+		},
+		0x00000040,  /* EmcZcalWaitCnt */
+		0x00020000,  /* EmcZcalInterval */
+		0x00000001,  /* EmcCfg bit 27PERIODIC_QRST */
+		0x80001221,  /* EmcMrs */
+		0x80100003,  /* EmcEmrs */
+		0x00000000,  /* EmcMrw1 */
+		0x00000001,  /* EmcCfg bit 28 DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		300000,     /* SDRAM frequency [kHz] */
+		{
+			0x00000010,  /* EmcRc */
+			0x0000004d,  /* EmcRfc */
+			0x0000000b,  /* EmcRas */
+			0x00000003,  /* EmcRp */
+			0x00000002,  /* EmcR2w */
+			0x00000008,  /* EmcW2r */
+			0x00000003,  /* EmcR2p */
+			0x00000009,  /* EmcW2p */
+			0x00000003,  /* EmcRdRcd */
+			0x00000002,  /* EmcWrRcd */
+			0x00000002,  /* EmcRrd */
+			0x00000001,  /* EmcRext */
+			0x00000000,  /* EmcWext */
+			0x00000004,  /* EmcWdv */
+			0x00000006,  /* EmcQUse */
+			0x00000004,  /* EmcQRst */
+			0x0000000a,  /* EmcQSafe */
+			0x0000000c,  /* EmcRdv */
+			0x000008e6,  /* EmcRefresh */
+			0x00000000,  /* EmcBurstRefreshNum */
+			0x00000240,  /* EmcPreRefreshReqCnt */
+			0x0000000a,  /* EmcPdEx2Wr */
+			0x00000008,  /* EmcPdEx2Rd */
+			0x00000007,  /* EmcPChg2Pden */
+			0x00000000,  /* EmcAct2Pden */
+			0x00000007,  /* EmcAr2Pden */
+			0x0000000e,  /* EmcRw2Pden */
+			0x000000b4,  /* EmcTxsr */
+			0x00000200,  /* EmcTxsrDll */
+			0x00000004,  /* EmcTcke */
+			0x00000010,  /* EmcTfaw */
+			0x00000000,  /* EmcTrpab */
+			0x00000004,  /* EmcTClkStable */
+			0x00000005,  /* EmcTClkStop */
+			0x00000927,  /* EmcTRefBw */
+			0x00000007,  /* EmcQUseExtra */
+			0x00000004,  /* EmcFbioCfg6 */
+			0x00000000,  /* EmcOdtWrite */
+			0x00000000,  /* EmcOdtRead */
+			0x00005288,  /* EmcFbioCfg5 */
+			0x002b00a4,  /* EmcCfgDigDll */
+			0x00008000,  /* EmcCfgDigDllPeriod */
+			0x00014000,  /* EmcDllXformDqs0 */
+			0x00014000,  /* EmcDllXformDqs1 */
+			0x00014000,  /* EmcDllXformDqs2 */
+			0x00014000,  /* EmcDllXformDqs3 */
+			0x00014000,  /* EmcDllXformDqs4 */
+			0x00014000,  /* EmcDllXformDqs5 */
+			0x00014000,  /* EmcDllXformDqs6 */
+			0x00014000,  /* EmcDllXformDqs7 */
+			0x00000000,  /* EmcDllXformQUse0 */
+			0x00000000,  /* EmcDllXformQUse1 */
+			0x00000000,  /* EmcDllXformQUse2 */
+			0x00000000,  /* EmcDllXformQUse3 */
+			0x00000000,  /* EmcDllXformQUse4 */
+			0x00000000,  /* EmcDllXformQUse5 */
+			0x00000000,  /* EmcDllXformQUse6 */
+			0x00000000,  /* EmcDllXformQUse7 */
+			0x00000000,  /* EmcDliTrimTxDqs0 */
+			0x00000000,  /* EmcDliTrimTxDqs1 */
+			0x00000000,  /* EmcDliTrimTxDqs2 */
+			0x00000000,  /* EmcDliTrimTxDqs3 */
+			0x00000000,  /* EmcDliTrimTxDqs4 */
+			0x00000000,  /* EmcDliTrimTxDqs5 */
+			0x00000000,  /* EmcDliTrimTxDqs6 */
+			0x00000000,  /* EmcDliTrimTxDqs7 */
+			0x00020000,  /* EmcDllXformDq0 */
+			0x00020000,  /* EmcDllXformDq1 */
+			0x00020000,  /* EmcDllXformDq2 */
+			0x00020000,  /* EmcDllXformDq3 */
+			0x000002a0,  /* EmcXm2CmdPadCtrl */
+			0x0800211c,  /* EmcXm2DqsPadCtrl2 */
+			0x00000000,  /* EmcXm2DqPadCtrl2 */
+			0x77fff884,  /* EmcXm2ClkPadCtrl */
+			0x01f1f508,  /* EmcXm2CompPadCtrl */
+			0x05057404,  /* EmcXm2VttGenPadCtrl */
+			0x54000007,  /* EmcXm2VttGenPadCtrl2 */
+			0x08000168,  /* EmcXm2QUsePadCtrl */
+			0x08000000,  /* EmcXm2DqsPadCtrl3 */
+			0x00000802,  /* EmcCttTermCtrl */
+			0x00020000,  /* EmcZcalInterval */
+			0x00000040,  /* EmcZcalWaitCnt */
+			0x0172000c,  /* EmcMrsWaitCnt */
+			0x001fffff,  /* EmcAutoCalInterval */
+			0x00000000,  /* EmcCtt */
+			0x00000000,  /* EmcCttDuration */
+			0x800012db,  /* EmcDynSelfRefControl */
+			0x00000004,  /* McEmemArbCfg */
+			0x80000037,  /* McEmemArbOutstandingReq */
+			0x00000001,  /* McEmemArbTimingRcd */
+			0x00000001,  /* McEmemArbTimingRp */
+			0x00000007,  /* McEmemArbTimingRc */
+			0x00000004,  /* McEmemArbTimingRas */
+			0x00000007,  /* McEmemArbTimingFaw */
+			0x00000001,  /* McEmemArbTimingRrd */
+			0x00000002,  /* McEmemArbTimingRap2Pre */
+			0x00000007,  /* McEmemArbTimingWap2Pre */
+			0x00000002,  /* McEmemArbTimingR2R */
+			0x00000002,  /* McEmemArbTimingW2W */
+			0x00000005,  /* McEmemArbTimingR2W */
+			0x00000006,  /* McEmemArbTimingW2R */
+			0x06030202,  /* McEmemArbDaTurns */
+			0x000a0507,  /* McEmemArbDaCovers */
+			0x70850e08,  /* McEmemArbMisc0 */
+			0x001f0000,  /* McEmemArbRing1Throttle */
+			0xe8000000,  /* EmcFbioSpare */
+			0xff00ff88,  /* EmcCfgRsv */
+		},
+		0x00000040,  /* EmcZcalWaitCnt */
+		0x00020000,  /* EmcZcalInterval */
+		0x00000001,  /* EmcCfg bit 27PERIODIC_QRST */
+		0x80000321,  /* EmcMrs */
+		0x80100002,  /* EmcEmrs */
+		0x00000000,  /* EmcMrw1 */
+		0x00000000,  /* EmcCfg bit 28 DYN_SELF_REF */
+	},
+	{
+		0x32,       /* Rev 3.2 */
+		333000,     /* SDRAM frequency [kHz] */
+		{
+			0x00000010,  /* EmcRc */
+			0x00000055,  /* EmcRfc */
+			0x0000000c,  /* EmcRas */
+			0x00000004,  /* EmcRp */
+			0x00000006,  /* EmcR2w */
+			0x00000008,  /* EmcW2r */
+			0x00000003,  /* EmcR2p */
+			0x00000009,  /* EmcW2p */
+			0x00000004,  /* EmcRdRcd */
+			0x00000003,  /* EmcWrRcd */
+			0x00000002,  /* EmcRrd */
+			0x00000001,  /* EmcRext */
+			0x00000000,  /* EmcWext */
+			0x00000004,  /* EmcWdv */
+			0x00000006,  /* EmcQUse */
+			0x00000004,  /* EmcQRst */
+			0x0000000a,  /* EmcQSafe */
+			0x0000000c,  /* EmcRdv */
+			0x000009e8,  /* EmcRefresh */
+			0x00000000,  /* EmcBurstRefreshNum */
+			0x0000027e,  /* EmcPreRefreshReqCnt */
+			0x0000000a,  /* EmcPdEx2Wr */
+			0x00000008,  /* EmcPdEx2Rd */
+			0x00000007,  /* EmcPChg2Pden */
+			0x00000000,  /* EmcAct2Pden */
+			0x00000007,  /* EmcAr2Pden */
+			0x0000000e,  /* EmcRw2Pden */
+			0x000000b4,  /* EmcTxsr */
+			0x00000200,  /* EmcTxsrDll */
+			0x00000004,  /* EmcTcke */
+			0x00000015,  /* EmcTfaw */
+			0x00000000,  /* EmcTrpab */
+			0x00000004,  /* EmcTClkStable */
+			0x00000005,  /* EmcTClkStop */
+			0x00000a28,  /* EmcTRefBw */
+			0x00000000,  /* EmcQUseExtra */
+			0x00000006,  /* EmcFbioCfg6 */
+			0x00000000,  /* EmcOdtWrite */
+			0x00000000,  /* EmcOdtRead */
+			0x00007088,  /* EmcFbioCfg5 */
+			0x002600a4,  /* EmcCfgDigDll */
+			0x00008000,  /* EmcCfgDigDllPeriod */
+			0x00014000,  /* EmcDllXformDqs0 */
+			0x00014000,  /* EmcDllXformDqs1 */
+			0x00014000,  /* EmcDllXformDqs2 */
+			0x00014000,  /* EmcDllXformDqs3 */
+			0x00014000,  /* EmcDllXformDqs4 */
+			0x00014000,  /* EmcDllXformDqs5 */
+			0x00014000,  /* EmcDllXformDqs6 */
+			0x00014000,  /* EmcDllXformDqs7 */
+			0x00000000,  /* EmcDllXformQUse0 */
+			0x00000000,  /* EmcDllXformQUse1 */
+			0x00000000,  /* EmcDllXformQUse2 */
+			0x00000000,  /* EmcDllXformQUse3 */
+			0x00000000,  /* EmcDllXformQUse4 */
+			0x00000000,  /* EmcDllXformQUse5 */
+			0x00000000,  /* EmcDllXformQUse6 */
+			0x00000000,  /* EmcDllXformQUse7 */
+			0x00000000,  /* EmcDliTrimTxDqs0 */
+			0x00000000,  /* EmcDliTrimTxDqs1 */
+			0x00000000,  /* EmcDliTrimTxDqs2 */
+			0x00000000,  /* EmcDliTrimTxDqs3 */
+			0x00000000,  /* EmcDliTrimTxDqs4 */
+			0x00000000,  /* EmcDliTrimTxDqs5 */
+			0x00000000,  /* EmcDliTrimTxDqs6 */
+			0x00000000,  /* EmcDliTrimTxDqs7 */
+			0x00020000,  /* EmcDllXformDq0 */
+			0x00020000,  /* EmcDllXformDq1 */
+			0x00020000,  /* EmcDllXformDq2 */
+			0x00020000,  /* EmcDllXformDq3 */
+			0x000002a0,  /* EmcXm2CmdPadCtrl */
+			0x0800013d,  /* EmcXm2DqsPadCtrl2 */
+			0x00000000,  /* EmcXm2DqPadCtrl2 */
+			0x77fff884,  /* EmcXm2ClkPadCtrl */
+			0x01f1f508,  /* EmcXm2CompPadCtrl */
+			0x05057404,  /* EmcXm2VttGenPadCtrl */
+			0x54000007,  /* EmcXm2VttGenPadCtrl2 */
+			0x080001e8,  /* EmcXm2QUsePadCtrl */
+			0x08000021,  /* EmcXm2DqsPadCtrl3 */
+			0x00000802,  /* EmcCttTermCtrl */
+			0x00020000,  /* EmcZcalInterval */
+			0x00000040,  /* EmcZcalWaitCnt */
+			0x016a000c,  /* EmcMrsWaitCnt */
+			0x001fffff,  /* EmcAutoCalInterval */
+			0x00000000,  /* EmcCtt */
+			0x00000000,  /* EmcCttDuration */
+			0x800014d2,  /* EmcDynSelfRefControl */
+			0x00000005,  /* McEmemArbCfg */
+			0x8000003c,  /* McEmemArbOutstandingReq */
+			0x00000001,  /* McEmemArbTimingRcd */
+			0x00000002,  /* McEmemArbTimingRp */
+			0x00000008,  /* McEmemArbTimingRc */
+			0x00000005,  /* McEmemArbTimingRas */
+			0x0000000a,  /* McEmemArbTimingFaw */
+			0x00000001,  /* McEmemArbTimingRrd */
+			0x00000002,  /* McEmemArbTimingRap2Pre */
+			0x00000007,  /* McEmemArbTimingWap2Pre */
+			0x00000002,  /* McEmemArbTimingR2R */
+			0x00000002,  /* McEmemArbTimingW2W */
+			0x00000005,  /* McEmemArbTimingR2W */
+			0x00000006,  /* McEmemArbTimingW2R */
+			0x06030202,  /* McEmemArbDaTurns */
+			0x000b0608,  /* McEmemArbDaCovers */
+			0x70850f09,  /* McEmemArbMisc0 */
+			0x001f0000,  /* McEmemArbRing1Throttle */
+			0xe8000000,  /* EmcFbioSpare */
+			0xff00ff88,  /* EmcCfgRsv */
+		},
+		0x00000040,  /* EmcZcalWaitCnt */
+		0x00020000,  /* EmcZcalInterval */
+		0x00000000,  /* EmcCfg bit 27PERIODIC_QRST */
+		0x80000321,  /* EmcMrs */
+		0x80100002,  /* EmcEmrs */
+		0x00000000,  /* EmcMrw1 */
+		0x00000000,  /* EmcCfg bit 28 DYN_SELF_REF */
+	},
+//400
+	{
+		0x32,       /* Rev 3.2 */
+		533000,     /* SDRAM frequency [kHz] */
+		{
+			0x0000001a,  /* EmcRc */
+			0x0000008b,  /* EmcRfc */
+			0x00000013,  /* EmcRas */
+			0x00000006,  /* EmcRp */
+			0x00000006,  /* EmcR2w */
+			0x0000000b,  /* EmcW2r */
+			0x00000003,  /* EmcR2p */
+			0x0000000e,  /* EmcW2p */
+			0x00000006,  /* EmcRdRcd */
+			0x00000006,  /* EmcWrRcd */
+			0x00000003,  /* EmcRrd */
+			0x00000001,  /* EmcRext */
+			0x00000000,  /* EmcWext */
+			0x00000006,  /* EmcWdv */
+			0x00000009,  /* EmcQUse */
+			0x00000007,  /* EmcQRst */
+			0x0000000a,  /* EmcQSafe */
+			0x0000000f,  /* EmcRdv */
+			0x0000100b,  /* EmcRefresh */
+			0x00000000,  /* EmcBurstRefreshNum */
+			0x000003ff,  /* EmcPreRefreshReqCnt */
+			0x0000000c,  /* EmcPdEx2Wr */
+			0x0000000c,  /* EmcPdEx2Rd */
+			0x00000007,  /* EmcPChg2Pden */
+			0x00000000,  /* EmcAct2Pden */
+			0x0000000a,  /* EmcAr2Pden */
+			0x00000012,  /* EmcRw2Pden */
+			0x000000b4,  /* EmcTxsr */
+			0x00000200,  /* EmcTxsrDll */
+			0x00000004,  /* EmcTcke */
+			0x0000001e,  /* EmcTfaw */
+			0x00000000,  /* EmcTrpab */
+			0x00000005,  /* EmcTClkStable */
+			0x00000006,  /* EmcTClkStop */
+			0x0000103e,  /* EmcTRefBw */
+			0x00000000,  /* EmcQUseExtra */
+			0x00000006,  /* EmcFbioCfg6 */
+			0x00000000,  /* EmcOdtWrite */
+			0x00000000,  /* EmcOdtRead */
+			0x00007088,  /* EmcFbioCfg5 */
+			0xf0120091,  /* EmcCfgDigDll */
+			0x00008000,  /* EmcCfgDigDllPeriod */
+			0x0000000a,  /* EmcDllXformDqs0 */
+			0x0000000a,  /* EmcDllXformDqs1 */
+			0x0000000a,  /* EmcDllXformDqs2 */
+			0x0000000a,  /* EmcDllXformDqs3 */
+			0x0000000a,  /* EmcDllXformDqs4 */
+			0x0000000a,  /* EmcDllXformDqs5 */
+			0x0000000a,  /* EmcDllXformDqs6 */
+			0x0000000a,  /* EmcDllXformDqs7 */
+			0x00000000,  /* EmcDllXformQUse0 */
+			0x00000000,  /* EmcDllXformQUse1 */
+			0x00000000,  /* EmcDllXformQUse2 */
+			0x00000000,  /* EmcDllXformQUse3 */
+			0x00000000,  /* EmcDllXformQUse4 */
+			0x00000000,  /* EmcDllXformQUse5 */
+			0x00000000,  /* EmcDllXformQUse6 */
+			0x00000000,  /* EmcDllXformQUse7 */
+			0x00000000,  /* EmcDliTrimTxDqs0 */
+			0x00000000,  /* EmcDliTrimTxDqs1 */
+			0x00000000,  /* EmcDliTrimTxDqs2 */
+			0x00000000,  /* EmcDliTrimTxDqs3 */
+			0x00000000,  /* EmcDliTrimTxDqs4 */
+			0x00000000,  /* EmcDliTrimTxDqs5 */
+			0x00000000,  /* EmcDliTrimTxDqs6 */
+			0x00000000,  /* EmcDliTrimTxDqs7 */
+			0x0000000a,  /* EmcDllXformDq0 */
+			0x0000000a,  /* EmcDllXformDq1 */
+			0x0000000a,  /* EmcDllXformDq2 */
+			0x0000000a,  /* EmcDllXformDq3 */
+			0x000002a0,  /* EmcXm2CmdPadCtrl */
+			0x0800013d,  /* EmcXm2DqsPadCtrl2 */
+			0x00000000,  /* EmcXm2DqPadCtrl2 */
+			0x77fff884,  /* EmcXm2ClkPadCtrl */
+			0x01f1f508,  /* EmcXm2CompPadCtrl */
+			0x05057404,  /* EmcXm2VttGenPadCtrl */
+			0x54000007,  /* EmcXm2VttGenPadCtrl2 */
+			0x080001e8,  /* EmcXm2QUsePadCtrl */
+			0x08000021,  /* EmcXm2DqsPadCtrl3 */
+			0x00000802,  /* EmcCttTermCtrl */
+			0x00020000,  /* EmcZcalInterval */
+			0x00000040,  /* EmcZcalWaitCnt */
+			0x016b000c,  /* EmcMrsWaitCnt */
+			0x001fffff,  /* EmcAutoCalInterval */
+			0x00000000,  /* EmcCtt */
+			0x00000000,  /* EmcCttDuration */
+			0x800020ae,  /* EmcDynSelfRefControl */
+			0x00000008,  /* McEmemArbCfg */
+			0x80000060,  /* McEmemArbOutstandingReq */
+			0x00000002,  /* McEmemArbTimingRcd */
+			0x00000003,  /* McEmemArbTimingRp */
+			0x0000000d,  /* McEmemArbTimingRc */
+			0x00000008,  /* McEmemArbTimingRas */
+			0x0000000f,  /* McEmemArbTimingFaw */
+			0x00000002,  /* McEmemArbTimingRrd */
+			0x00000002,  /* McEmemArbTimingRap2Pre */
+			0x00000009,  /* McEmemArbTimingWap2Pre */
+			0x00000002,  /* McEmemArbTimingR2R */
+			0x00000002,  /* McEmemArbTimingW2W */
+			0x00000005,  /* McEmemArbTimingR2W */
+			0x00000006,  /* McEmemArbTimingW2R */
+			0x06030202,  /* McEmemArbDaTurns */
+			0x000f080d,  /* McEmemArbDaCovers */
+			0x70c8180e,  /* McEmemArbMisc0 */
+			0x001f0000,  /* McEmemArbRing1Throttle */
+			0xe8000000,  /* EmcFbioSpare */
+			0xff00ff88,  /* EmcCfgRsv */
+		},
+		0x00000040,  /* EmcZcalWaitCnt */
+		0x00020000,  /* EmcZcalInterval */
+		0x00000000,  /* EmcCfg bit 27PERIODIC_QRST */
+		0x80000931,  /* EmcMrs */
+		0x80100002,  /* EmcEmrs */
+		0x00000000,  /* EmcMrw1 */
+		0x00000000,  /* EmcCfg bit 28 DYN_SELF_REF */
+	},
+#if 0
+	{
+		0x32,       /* Rev 3.2 */
+		667000,     /* SDRAM frequency [kHz] */
+		{
+			0x0000001f,  /* EmcRc */
+			0x000000ac,  /* EmcRfc */
+			0x00000016,  /* EmcRas */
+			0x00000007,  /* EmcRp */
+			0x00000006,  /* EmcR2w */
+			0x0000000b,  /* EmcW2r */
+			0x00000003,  /* EmcR2p */
+			0x00000010,  /* EmcW2p */
+			0x00000007,  /* EmcRdRcd */
+			0x00000007,  /* EmcWrRcd */
+			0x00000003,  /* EmcRrd */
+			0x00000001,  /* EmcRext */
+			0x00000000,  /* EmcWext */
+			0x00000006,  /* EmcWdv */
+			0x00000009,  /* EmcQUse */
+			0x00000007,  /* EmcQRst */
+			0x0000000a,  /* EmcQSafe */
+			0x0000000f,  /* EmcRdv */
+			0x00001410,  /* EmcRefresh */
+			0x00000000,  /* EmcBurstRefreshNum */
+			0x00000504,  /* EmcPreRefreshReqCnt */
+			0x0000000e,  /* EmcPdEx2Wr */
+			0x0000000e,  /* EmcPdEx2Rd */
+			0x00000007,  /* EmcPChg2Pden */
+			0x00000000,  /* EmcAct2Pden */
+			0x0000000c,  /* EmcAr2Pden */
+			0x00000015,  /* EmcRw2Pden */
+			0x000000b4,  /* EmcTxsr */
+			0x00000200,  /* EmcTxsrDll */
+			0x00000004,  /* EmcTcke */
+			0x0000001e,  /* EmcTfaw */
+			0x00000000,  /* EmcTrpab */
+			0x00000006,  /* EmcTClkStable */
+			0x00000007,  /* EmcTClkStop */
+			0x00001450,  /* EmcTRefBw */
+			0x0000000a,  /* EmcQUseExtra */
+			0x00000006,  /* EmcFbioCfg6 */
+			0x00000000,  /* EmcOdtWrite */
+			0x00000000,  /* EmcOdtRead */
+			0x00005088,  /* EmcFbioCfg5 */
+			0xf00b0191,  /* EmcCfgDigDll */
+			0x00008000,  /* EmcCfgDigDllPeriod */
+			0x0000000a,  /* EmcDllXformDqs0 */
+			0x0000000a,  /* EmcDllXformDqs1 */
+			0x0000000a,  /* EmcDllXformDqs2 */
+			0x0000000a,  /* EmcDllXformDqs3 */
+			0x0000000a,  /* EmcDllXformDqs4 */
+			0x0000000a,  /* EmcDllXformDqs5 */
+			0x0000000a,  /* EmcDllXformDqs6 */
+			0x0000000a,  /* EmcDllXformDqs7 */
+			0x00000000,  /* EmcDllXformQUse0 */
+			0x00000000,  /* EmcDllXformQUse1 */
+			0x00000000,  /* EmcDllXformQUse2 */
+			0x00000000,  /* EmcDllXformQUse3 */
+			0x00000000,  /* EmcDllXformQUse4 */
+			0x00000000,  /* EmcDllXformQUse5 */
+			0x00000000,  /* EmcDllXformQUse6 */
+			0x00000000,  /* EmcDllXformQUse7 */
+			0x00000000,  /* EmcDliTrimTxDqs0 */
+			0x00000000,  /* EmcDliTrimTxDqs1 */
+			0x00000000,  /* EmcDliTrimTxDqs2 */
+			0x00000000,  /* EmcDliTrimTxDqs3 */
+			0x00000000,  /* EmcDliTrimTxDqs4 */
+			0x00000000,  /* EmcDliTrimTxDqs5 */
+			0x00000000,  /* EmcDliTrimTxDqs6 */
+			0x00000000,  /* EmcDliTrimTxDqs7 */
+			0x0000000a,  /* EmcDllXformDq0 */
+			0x0000000a,  /* EmcDllXformDq1 */
+			0x0000000a,  /* EmcDllXformDq2 */
+			0x0000000a,  /* EmcDllXformDq3 */
+			0x000002a0,  /* EmcXm2CmdPadCtrl */
+			0x0800013d,  /* EmcXm2DqsPadCtrl2 */
+			0x22220000,  /* EmcXm2DqPadCtrl2 */
+			0x77fff884,  /* EmcXm2ClkPadCtrl */
+			0x01f1f508,  /* EmcXm2CompPadCtrl */
+			0x07077404,  /* EmcXm2VttGenPadCtrl */
+			0x54000000,  /* EmcXm2VttGenPadCtrl2 */
+			0x080001e8,  /* EmcXm2QUsePadCtrl */
+			0x08000021,  /* EmcXm2DqsPadCtrl3 */
+			0x00000802,  /* EmcCttTermCtrl */
+			0x00020000,  /* EmcZcalInterval */
+			0x00000040,  /* EmcZcalWaitCnt */
+			0x0196000c,  /* EmcMrsWaitCnt */
+			0x001fffff,  /* EmcAutoCalInterval */
+			0x00000000,  /* EmcCtt */
+			0x00000000,  /* EmcCttDuration */
+			0x800028a0,  /* EmcDynSelfRefControl */
+			0x0000000a,  /* McEmemArbCfg */
+			0x80000078,  /* McEmemArbOutstandingReq */
+			0x00000003,  /* McEmemArbTimingRcd */
+			0x00000004,  /* McEmemArbTimingRp */
+			0x00000010,  /* McEmemArbTimingRc */
+			0x0000000a,  /* McEmemArbTimingRas */
+			0x0000000f,  /* McEmemArbTimingFaw */
+			0x00000002,  /* McEmemArbTimingRrd */
+			0x00000003,  /* McEmemArbTimingRap2Pre */
+			0x0000000b,  /* McEmemArbTimingWap2Pre */
+			0x00000002,  /* McEmemArbTimingR2R */
+			0x00000002,  /* McEmemArbTimingW2W */
+			0x00000004,  /* McEmemArbTimingR2W */
+			0x00000007,  /* McEmemArbTimingW2R */
+			0x07040202,  /* McEmemArbDaTurns */
+			0x00130b10,  /* McEmemArbDaCovers */
+			0x70ea1e11,  /* McEmemArbMisc0 */
+			0x001f0000,  /* McEmemArbRing1Throttle */
+			0xe8000000,  /* EmcFbioSpare */
+			0xff00ff49,  /* EmcCfgRsv */
+		},
+		0x00000040,  /* EmcZcalWaitCnt */
+		0x00020000,  /* EmcZcalInterval */
+		0x00000001,  /* EmcCfg bit 27PERIODIC_QRST */
+		0x80000b51,  /* EmcMrs */
+		0x80100002,  /* EmcEmrs */
+		0x00000000,  /* EmcMrw1 */
+		0x00000000,  /* EmcCfg bit 28 DYN_SELF_REF */
+	},
+//750
+#endif
+};
+
+int apalis_t30_emc_init(void)
+{
+#if 1
+	tegra_init_emc(apalis_t30_emc_tables_mt41k256m16re_15e,
+			ARRAY_SIZE(apalis_t30_emc_tables_mt41k256m16re_15e));
+#else
+	tegra_init_emc(cardhu_emc_tables_h5tc2g_a2,
+			ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2));
+#endif
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis_t30-panel.c b/arch/arm/mach-tegra/board-apalis_t30-panel.c
new file mode 100644
index 000000000000..04624110bce3
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30-panel.c
@@ -0,0 +1,784 @@
+/*
+ * arch/arm/mach-tegra/board-apalis_t30-panel.c
+ *
+ * Copyright (c) 2013, Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <asm/atomic.h>
+#include <asm/mach-types.h>
+
+#include <linux/delay.h>
+#include <linux/earlysuspend.h>
+#include <linux/gpio.h>
+#include <linux/ion.h>
+#include <linux/nvhost.h>
+#include <linux/nvmap.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <linux/tegra_ion.h>
+
+#include <mach/dc.h>
+#include <mach/fb.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/smmu.h>
+
+#include "board.h"
+#include "board-apalis_t30.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "tegra3_host1x_devices.h"
+
+#define apalis_t30_bl_enb	TEGRA_GPIO_PV2	/* BL_ON */
+#define apalis_t30_hdmi_hpd	TEGRA_GPIO_PN7	/* HDMI_INT_N */
+
+static struct regulator *apalis_t30_hdmi_pll = NULL;
+static struct regulator *apalis_t30_hdmi_reg = NULL;
+static struct regulator *apalis_t30_hdmi_vddio = NULL;
+
+static int apalis_t30_backlight_init(struct device *dev) {
+	int ret;
+
+	ret = gpio_request(apalis_t30_bl_enb, "BL_ON");
+	if (ret < 0)
+		return ret;
+
+	ret = gpio_direction_output(apalis_t30_bl_enb, 1);
+	if (ret < 0)
+		gpio_free(apalis_t30_bl_enb);
+
+	return ret;
+};
+
+static void apalis_t30_backlight_exit(struct device *dev) {
+	gpio_set_value(apalis_t30_bl_enb, 0);
+	gpio_free(apalis_t30_bl_enb);
+}
+
+static int apalis_t30_backlight_notify(struct device *dev, int brightness)
+{
+	struct platform_pwm_backlight_data *pdata = dev->platform_data;
+
+	gpio_set_value(apalis_t30_bl_enb, !!brightness);
+
+	/* unified TFT interface displays (e.g. EDT ET070080DH6) LEDCTRL pin
+	   with inverted behaviour (e.g. 0V brightest vs. 3.3V darkest) */
+	if (brightness)	return pdata->max_brightness - brightness;
+	else return brightness;
+}
+
+static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info);
+
+static struct platform_pwm_backlight_data apalis_t30_backlight_data = {
+	.pwm_id		= 0,
+	.max_brightness	= 255,
+	.dft_brightness	= 127,
+	.pwm_period_ns	= 1000000, /* 1 kHz */
+	.init		= apalis_t30_backlight_init,
+	.exit		= apalis_t30_backlight_exit,
+	.notify		= apalis_t30_backlight_notify,
+	/* Only toggle backlight on fb blank notifications for disp1 */
+	.check_fb	= apalis_t30_disp1_check_fb,
+};
+
+static struct platform_device apalis_t30_backlight_device = {
+	.name	= "pwm-backlight",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &apalis_t30_backlight_data,
+	},
+};
+
+static int apalis_t30_panel_enable(void)
+{
+	return 0;
+}
+
+static int apalis_t30_panel_disable(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA_DC
+static int apalis_t30_hdmi_vddio_enable(void)
+{
+	int ret;
+	if (!apalis_t30_hdmi_vddio) {
+		apalis_t30_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
+		if (IS_ERR_OR_NULL(apalis_t30_hdmi_vddio)) {
+			ret = PTR_ERR(apalis_t30_hdmi_vddio);
+			pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
+			apalis_t30_hdmi_vddio = NULL;
+			return ret;
+		}
+	}
+	ret = regulator_enable(apalis_t30_hdmi_vddio);
+	if (ret < 0) {
+		pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
+		regulator_put(apalis_t30_hdmi_vddio);
+		apalis_t30_hdmi_vddio = NULL;
+		return ret;
+	}
+	return ret;
+}
+
+static int apalis_t30_hdmi_vddio_disable(void)
+{
+	if (apalis_t30_hdmi_vddio) {
+		regulator_disable(apalis_t30_hdmi_vddio);
+		regulator_put(apalis_t30_hdmi_vddio);
+		apalis_t30_hdmi_vddio = NULL;
+	}
+	return 0;
+}
+
+static int apalis_t30_hdmi_enable(void)
+{
+	int ret;
+	if (!apalis_t30_hdmi_reg) {
+		apalis_t30_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
+		if (IS_ERR_OR_NULL(apalis_t30_hdmi_reg)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+			apalis_t30_hdmi_reg = NULL;
+			return PTR_ERR(apalis_t30_hdmi_reg);
+		}
+	}
+	ret = regulator_enable(apalis_t30_hdmi_reg);
+	if (ret < 0) {
+		pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+		return ret;
+	}
+	if (!apalis_t30_hdmi_pll) {
+		apalis_t30_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
+		if (IS_ERR_OR_NULL(apalis_t30_hdmi_pll)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+			apalis_t30_hdmi_pll = NULL;
+			regulator_put(apalis_t30_hdmi_reg);
+			apalis_t30_hdmi_reg = NULL;
+			return PTR_ERR(apalis_t30_hdmi_pll);
+		}
+	}
+	ret = regulator_enable(apalis_t30_hdmi_pll);
+	if (ret < 0) {
+		pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+		return ret;
+	}
+	return 0;
+}
+
+static int apalis_t30_hdmi_disable(void)
+{
+	regulator_disable(apalis_t30_hdmi_reg);
+	regulator_put(apalis_t30_hdmi_reg);
+	apalis_t30_hdmi_reg = NULL;
+
+	regulator_disable(apalis_t30_hdmi_pll);
+	regulator_put(apalis_t30_hdmi_pll);
+	apalis_t30_hdmi_pll = NULL;
+	return 0;
+}
+static struct resource apalis_t30_disp1_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_GENERAL,
+		.end	= INT_DISPLAY_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY_BASE,
+		.end	= TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.start	= 0,	/* Filled in by apalis_t30_panel_init() */
+		.end	= 0,	/* Filled in by apalis_t30_panel_init() */
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource apalis_t30_disp2_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_B_GENERAL,
+		.end	= INT_DISPLAY_B_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY2_BASE,
+		.end	= TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.flags	= IORESOURCE_MEM,
+		.start	= 0,
+		.end	= 0,
+	},
+	{
+		.name	= "hdmi_regs",
+		.start	= TEGRA_HDMI_BASE,
+		.end	= TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+#endif /* CONFIG_TEGRA_DC */
+
+static struct tegra_dc_mode apalis_t30_panel_modes[] = {
+#ifdef TEGRA_FB_VGA
+	{
+		/* 640x480p 60hz: EIA/CEA-861-B Format 1 */
+		.pclk		= 25175000,	/* pixclock */
+		.h_ref_to_sync	= 8,
+		.v_ref_to_sync	= 2,
+		.h_sync_width	= 96,		/* hsync_len */
+		.v_sync_width	= 2,		/* vsync_len */
+		.h_back_porch	= 48,		/* left_margin */
+		.v_back_porch	= 33,		/* upper_margin */
+		.h_active	= 640,
+		.v_active	= 480,
+		.h_front_porch	= 16,		/* right_margin */
+		.v_front_porch	= 10,		/* lower_margin */
+	},
+#else /* TEGRA_FB_VGA */
+	{
+		/* 800x480@60 (e.g. EDT ET070080DH6) */
+		.pclk		= 32460000,
+		.h_ref_to_sync	= 1,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 64,
+		.v_sync_width	= 3,
+		.h_back_porch	= 128,
+		.v_back_porch	= 22,
+		.h_active	= 800,
+		.v_active	= 480,
+		.h_front_porch	= 64,
+		.v_front_porch	= 20,
+	},
+	{
+		/* 800x600@60 */
+		.pclk		= 39272727,
+		.h_sync_width	= 80,
+		.v_sync_width	= 2,
+		.h_back_porch	= 160,
+		.v_back_porch	= 21,
+		.h_active	= 800,
+		.v_active	= 600,
+		.h_front_porch	= 16,
+		.v_front_porch	= 1,
+	},
+	{
+		/* 1024x768@60 */
+		.pclk		= 78800000,
+		.h_sync_width	= 96,
+		.v_sync_width	= 3,
+		.h_back_porch	= 176,
+		.v_back_porch	= 28,
+		.h_active	= 1024,
+		.v_active	= 768,
+		.h_front_porch	= 16,
+		.v_front_porch	= 1,
+	},
+	{
+		/* 1024x768@75 */
+		.pclk		= 82000000,
+		.h_sync_width	= 104,
+		.v_sync_width	= 4,
+		.h_back_porch	= 168,
+		.v_back_porch	= 34,
+		.h_active	= 1024,
+		.v_active	= 768,
+		.h_front_porch	= 64,
+		.v_front_porch	= 3,
+	},
+	{
+		/* 1280x720@60 */
+		.pclk		= 74250000,
+		.h_ref_to_sync	= 1,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 40,
+		.v_sync_width	= 5,
+		.h_back_porch	= 220,
+		.v_back_porch	= 20,
+		.h_active	= 1280,
+		.v_active	= 720,
+		.h_front_porch	= 110,
+		.v_front_porch	= 5,
+//high active sync polarities
+	},
+	{
+		/* 1280x1024@60 */
+		.pclk		= 108000000,
+//		.h_ref_to_sync	= 1,
+//		.v_ref_to_sync	= 1,
+		.h_sync_width	= 144,
+		.v_sync_width	= 3,
+		.h_back_porch	= 248,
+		.v_back_porch	= 38,
+		.h_active	= 1280,
+		.v_active	= 1024,
+		.h_front_porch	= 16,
+		.v_front_porch	= 1,
+//high active sync polarities
+	},
+	{
+		/* 1366x768@60 */
+		.pclk		= 72072000,
+		.h_ref_to_sync	= 11,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 58,
+		.v_sync_width	= 4,
+		.h_back_porch	= 58,
+		.v_back_porch	= 4,
+		.h_active	= 1366,
+		.v_active	= 768,
+		.h_front_porch	= 58,
+		.v_front_porch	= 4,
+	},
+	{
+		/* 1600x1200@60 */
+		.pclk		= 162000000,
+//		.h_ref_to_sync	= 1,
+//		.v_ref_to_sync	= 1,
+		.h_sync_width	= 192,
+		.v_sync_width	= 3,
+		.h_back_porch	= 304,
+		.v_back_porch	= 46,
+		.h_active	= 1600,
+		.v_active	= 1200,
+		.h_front_porch	= 64,
+		.v_front_porch	= 1,
+//high active sync polarities
+	},
+	{
+		.pclk		= 119000000,
+		.h_ref_to_sync	= 1,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 32,
+		.v_sync_width	= 6,
+		.h_back_porch	= 80,
+		.v_back_porch	= 21,
+		.h_active	= 1680,
+		.v_active	= 1050,
+		.h_front_porch	= 48,
+		.v_front_porch	= 3,
+	},
+	{
+		/* 1680x1050@60 */
+		.pclk		= 147140000,
+//		.h_ref_to_sync	= 1,
+//		.v_ref_to_sync	= 1,
+		.h_sync_width	= 184,
+		.v_sync_width	= 3,
+		.h_back_porch	= 288,
+		.v_back_porch	= 33,
+		.h_active	= 1680,
+		.v_active	= 1050,
+		.h_front_porch	= 104,
+		.v_front_porch	= 1,
+//high active vertical sync polarity
+	},
+	{
+		/* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
+		.pclk		= 148500000,
+		.h_ref_to_sync	= 11,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 44,
+		.v_sync_width	= 5,
+		.h_back_porch	= 148,
+		.v_back_porch	= 36,
+		.h_active	= 1920,
+		.v_active	= 1080,
+		.h_front_porch	= 88,
+		.v_front_porch	= 4,
+//high active sync polarities
+	},
+	{
+		.pclk		= 154000000,
+		.h_ref_to_sync	= 11,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 32,
+		.v_sync_width	= 6,
+		.h_back_porch	= 80,
+		.v_back_porch	= 26,
+		.h_active	= 1920,
+		.v_active	= 1200,
+		.h_front_porch	= 48,
+		.v_front_porch	= 3,
+	},
+
+	/* portrait modes */
+
+	{
+		.pclk		= 18000000,
+		.h_ref_to_sync	= 8,
+		.v_ref_to_sync	= 2,
+		.h_sync_width	= 4,
+		.v_sync_width	= 1,
+		.h_back_porch	= 20,
+		.v_back_porch	= 7,
+		.h_active	= 480,
+		.v_active	= 640,
+		.h_front_porch	= 8,
+		.v_front_porch	= 8,
+	},
+	{
+		.pclk		= 10000000,
+		.h_ref_to_sync	= 4,
+		.v_ref_to_sync	= 1,
+		.h_sync_width	= 16,
+		.v_sync_width	= 1,
+		.h_back_porch	= 32,
+		.v_back_porch	= 1,
+		.h_active	= 540,
+		.v_active	= 960,
+		.h_front_porch	= 32,
+		.v_front_porch	= 2,
+	},
+	{
+		.pclk		= 61417000,
+		.h_ref_to_sync	= 2,
+		.v_ref_to_sync	= 2,
+		.h_sync_width	= 4,
+		.v_sync_width	= 4,
+		.h_back_porch	= 100,
+		.v_back_porch	= 14,
+		.h_active	= 720,
+		.v_active	= 1280,
+		.h_front_porch	= 4,
+		.v_front_porch	= 4,
+	},
+#endif /* TEGRA_FB_VGA */
+};
+
+#ifdef CONFIG_TEGRA_DC
+static struct tegra_fb_data apalis_t30_fb_data = {
+	.win		= 0,
+#ifdef TEGRA_FB_VGA
+	.xres		= 640,
+	.yres		= 480,
+#else /* TEGRA_FB_VGA */
+	.xres		= 800,
+	.yres		= 480,
+#endif /* TEGRA_FB_VGA */
+	.bits_per_pixel	= 16,
+	.flags		= TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_fb_data apalis_t30_hdmi_fb_data = {
+	.win		= 0,
+	.xres		= 640,
+	.yres		= 480,
+	.bits_per_pixel	= 16,
+	.flags		= TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_out_pin apalis_t30_dc_out_pins[] = {
+	{
+		.name	= TEGRA_DC_OUT_PIN_H_SYNC,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+	{
+		.name	= TEGRA_DC_OUT_PIN_V_SYNC,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+	{
+		.name	= TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+};
+
+static struct tegra_dc_out apalis_t30_disp1_out = {
+	.type			= TEGRA_DC_OUT_RGB,
+	.parent_clk		= "pll_d_out0",
+	.parent_clk_backup	= "pll_d2_out0",
+
+	.align			= TEGRA_DC_ALIGN_MSB,
+	.order			= TEGRA_DC_ORDER_RED_BLUE,
+	.depth			= 18,
+	.dither			= TEGRA_DC_ORDERED_DITHER,
+
+	.modes			= apalis_t30_panel_modes,
+	.n_modes		= ARRAY_SIZE(apalis_t30_panel_modes),
+
+	.out_pins		= apalis_t30_dc_out_pins,
+	.n_out_pins		= ARRAY_SIZE(apalis_t30_dc_out_pins),
+
+	.enable			= apalis_t30_panel_enable,
+	.disable		= apalis_t30_panel_disable,
+};
+
+static struct tegra_dc_out apalis_t30_disp2_out = {
+	.type		= TEGRA_DC_OUT_HDMI,
+	.flags		= TEGRA_DC_OUT_HOTPLUG_HIGH,
+	.parent_clk	= "pll_d2_out0",
+
+	.dcc_bus	= 3,
+	.hotplug_gpio	= apalis_t30_hdmi_hpd,
+
+	.max_pixclock	= KHZ2PICOS(148500),
+
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+
+	.enable		= apalis_t30_hdmi_enable,
+	.disable	= apalis_t30_hdmi_disable,
+
+	.postsuspend	= apalis_t30_hdmi_vddio_disable,
+	.hotplug_init	= apalis_t30_hdmi_vddio_enable,
+};
+
+static struct tegra_dc_platform_data apalis_t30_disp1_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &apalis_t30_disp1_out,
+	.emc_clk_rate	= 300000000,
+	.fb		= &apalis_t30_fb_data,
+};
+
+static struct tegra_dc_platform_data apalis_t30_disp2_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &apalis_t30_disp2_out,
+	.fb		= &apalis_t30_hdmi_fb_data,
+	.emc_clk_rate	= 300000000,
+};
+
+static struct nvhost_device apalis_t30_disp1_device = {
+	.name		= "tegradc",
+	.id		= 0,
+	.resource	= apalis_t30_disp1_resources,
+	.num_resources	= ARRAY_SIZE(apalis_t30_disp1_resources),
+	.dev = {
+		.platform_data = &apalis_t30_disp1_pdata,
+	},
+};
+
+static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+	return info->device == &apalis_t30_disp1_device.dev;
+}
+
+static struct nvhost_device apalis_t30_disp2_device = {
+	.name		= "tegradc",
+	.id		= 1,
+	.resource	= apalis_t30_disp2_resources,
+	.num_resources	= ARRAY_SIZE(apalis_t30_disp2_resources),
+	.dev = {
+		.platform_data = &apalis_t30_disp2_pdata,
+	},
+};
+#else /* CONFIG_TEGRA_DC */
+static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+	return 0;
+}
+#endif /* CONFIG_TEGRA_DC */
+
+#if defined(CONFIG_TEGRA_NVMAP)
+static struct nvmap_platform_carveout apalis_t30_carveouts[] = {
+	[0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
+	[1] = {
+		.name		= "generic-0",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
+		.base		= 0,	/* Filled in by apalis_t30_panel_init() */
+		.size		= 0,	/* Filled in by apalis_t30_panel_init() */
+		.buddy_size	= SZ_32K,
+	},
+};
+
+static struct nvmap_platform_data apalis_t30_nvmap_data = {
+	.carveouts	= apalis_t30_carveouts,
+	.nr_carveouts	= ARRAY_SIZE(apalis_t30_carveouts),
+};
+
+static struct platform_device apalis_t30_nvmap_device = {
+	.name	= "tegra-nvmap",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &apalis_t30_nvmap_data,
+	},
+};
+#endif /* CONFIG_TEGRA_NVMAP */
+
+#if defined(CONFIG_ION_TEGRA)
+static struct platform_device tegra_iommu_device = {
+	.name = "tegra_iommu_device",
+	.id = -1,
+	.dev = {
+		.platform_data = (void *)((1 << HWGRP_COUNT) - 1),
+	},
+};
+
+static struct ion_platform_data tegra_ion_data = {
+	.nr = 4,
+	.heaps = {
+		{
+			.type = ION_HEAP_TYPE_CARVEOUT,
+			.id = TEGRA_ION_HEAP_CARVEOUT,
+			.name = "carveout",
+			.base = 0,
+			.size = 0,
+		},
+		{
+			.type = ION_HEAP_TYPE_CARVEOUT,
+			.id = TEGRA_ION_HEAP_IRAM,
+			.name = "iram",
+			.base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+			.size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+		},
+		{
+			.type = ION_HEAP_TYPE_CARVEOUT,
+			.id = TEGRA_ION_HEAP_VPR,
+			.name = "vpr",
+			.base = 0,
+			.size = 0,
+		},
+		{
+			.type = ION_HEAP_TYPE_IOMMU,
+			.id = TEGRA_ION_HEAP_IOMMU,
+			.name = "iommu",
+			.base = TEGRA_SMMU_BASE,
+			.size = TEGRA_SMMU_SIZE,
+			.priv = &tegra_iommu_device.dev,
+		},
+	},
+};
+
+static struct platform_device tegra_ion_device = {
+	.name = "ion-tegra",
+	.id = -1,
+	.dev = {
+		.platform_data = &tegra_ion_data,
+	},
+};
+#endif /* CONFIG_ION_TEGRA */
+
+static struct platform_device *apalis_t30_gfx_devices[] __initdata = {
+#if defined(CONFIG_TEGRA_NVMAP)
+	&apalis_t30_nvmap_device,
+#endif
+#if defined(CONFIG_ION_TEGRA)
+	&tegra_ion_device,
+#endif
+	&tegra_pwfm0_device,
+	&apalis_t30_backlight_device,
+};
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+/* put early_suspend/late_resume handlers here for the display in order
+ * to keep the code out of the display driver, keeping it closer to upstream
+ */
+struct early_suspend apalis_t30_panel_early_suspender;
+
+static void apalis_t30_panel_early_suspend(struct early_suspend *h)
+{
+	/* power down LCD, add use a black screen for HDMI */
+	if (num_registered_fb > 0)
+		fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
+	if (num_registered_fb > 1)
+		fb_blank(registered_fb[1], FB_BLANK_NORMAL);
+}
+
+static void apalis_t30_panel_late_resume(struct early_suspend *h)
+{
+	unsigned i;
+	for (i = 0; i < num_registered_fb; i++)
+		fb_blank(registered_fb[i], FB_BLANK_UNBLANK);
+}
+#endif /* CONFIG_HAS_EARLYSUSPEND */
+
+int __init apalis_t30_panel_init(void)
+{
+	int err = 0;
+	struct resource *res;
+	void __iomem *to_io;
+
+	/* enable hdmi hotplug gpio for hotplug detection */
+	gpio_request(apalis_t30_hdmi_hpd, "hdmi_hpd");
+	gpio_direction_input(apalis_t30_hdmi_hpd);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	apalis_t30_panel_early_suspender.suspend = apalis_t30_panel_early_suspend;
+	apalis_t30_panel_early_suspender.resume = apalis_t30_panel_late_resume;
+	apalis_t30_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+	register_early_suspend(&apalis_t30_panel_early_suspender);
+#endif /* CONFIG_HAS_EARLYSUSPEND */
+
+#ifdef CONFIG_TEGRA_NVMAP
+	apalis_t30_carveouts[1].base = tegra_carveout_start;
+	apalis_t30_carveouts[1].size = tegra_carveout_size;
+#endif /* CONFIG_TEGRA_NVMAP */
+
+#ifdef CONFIG_ION_TEGRA
+	tegra_ion_data.heaps[0].base = tegra_carveout_start;
+	tegra_ion_data.heaps[0].size = tegra_carveout_size;
+#endif /* CONFIG_ION_TEGRA */
+
+#ifdef CONFIG_TEGRA_GRHOST
+	err = tegra3_register_host1x_devices();
+	if (err)
+		return err;
+#endif /* CONFIG_TEGRA_GRHOST */
+
+	err = platform_add_devices(apalis_t30_gfx_devices,
+				ARRAY_SIZE(apalis_t30_gfx_devices));
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+	res = nvhost_get_resource_byname(&apalis_t30_disp1_device,
+					 IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb_start;
+	res->end = tegra_fb_start + tegra_fb_size - 1;
+
+	res = nvhost_get_resource_byname(&apalis_t30_disp2_device,
+					 IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb2_start;
+	res->end = tegra_fb2_start + tegra_fb2_size - 1;
+#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */
+
+	/* Make sure LVDS framebuffer is cleared. */
+	to_io = ioremap(tegra_fb_start, tegra_fb_size);
+	if (to_io) {
+		memset(to_io, 0, tegra_fb_size);
+		iounmap(to_io);
+	} else pr_err("%s: Failed to map LVDS framebuffer\n", __func__);
+
+	/* Make sure HDMI framebuffer is cleared.
+	   Note: this seems to fix a tegradc.1 initialisation race in case of
+	   framebuffer console as well. */
+	to_io = ioremap(tegra_fb2_start, tegra_fb2_size);
+	if (to_io) {
+		memset(to_io, 0, tegra_fb2_size);
+		iounmap(to_io);
+	} else pr_err("%s: Failed to map HDMI framebuffer\n", __func__);
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+	if (!err)
+		err = nvhost_device_register(&apalis_t30_disp1_device);
+
+	if (!err)
+		err = nvhost_device_register(&apalis_t30_disp2_device);
+#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
+	if (!err)
+		err = nvhost_device_register(&nvavp_device);
+#endif
+	return err;
+}
diff --git a/arch/arm/mach-tegra/board-apalis_t30-pinmux.c b/arch/arm/mach-tegra/board-apalis_t30-pinmux.c
new file mode 100644
index 000000000000..a04a15587129
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30-pinmux.c
@@ -0,0 +1,487 @@
+/*
+ * arch/arm/mach-tegra/board-apalis_t30-pinmux.c
+ *
+ * Copyright (C) 2013 Toradex, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <mach/pinmux.h>
+
+#include "board-apalis_t30.h"
+#include "board.h"
+#include "gpio-names.h"
+
+#define DEFAULT_DRIVE(_name)					\
+	{							\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
+		.hsm = TEGRA_HSM_DISABLE,			\
+		.schmitt = TEGRA_SCHMITT_ENABLE,		\
+		.drive = TEGRA_DRIVE_DIV_1,			\
+		.pull_down = TEGRA_PULL_31,			\
+		.pull_up = TEGRA_PULL_31,			\
+		.slew_rising = TEGRA_SLEW_SLOWEST,		\
+		.slew_falling = TEGRA_SLEW_SLOWEST,		\
+	}
+
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+	{                                               \
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+		.hsm = TEGRA_HSM_##_hsm,                    \
+		.schmitt = TEGRA_SCHMITT_##_schmitt,        \
+		.drive = TEGRA_DRIVE_##_drive,              \
+		.pull_down = TEGRA_PULL_##_pulldn_drive,    \
+		.pull_up = TEGRA_PULL_##_pullup_drive,		\
+		.slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+		.slew_falling = TEGRA_SLEW_##_pullup_slew,	\
+	}
+
+static __initdata struct tegra_drive_pingroup_config apalis_t30_drive_pinmux[] = {
+	/* DEFAULT_DRIVE(<pin_group>), */
+
+	/* Audio codec */
+	SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* All I2C pins are driven to maximum drive strength */
+
+	/* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */
+	SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+	SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+		    touch screen controller */
+	SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* SDMMC2 */
+	SET_DRIVE(AO2,	DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+	/* eMMC on SDMMC4 */
+	SET_DRIVE(GMA, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+	SET_DRIVE(GMB, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+	SET_DRIVE(GMC, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+	SET_DRIVE(GMD, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)	\
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+/* TRISTATE here means output driver is tri-stated */ \
+		.tristate	= TEGRA_TRI_##_tri,		\
+/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_DEFAULT,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_##_od,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_##_ioreset	\
+	}
+
+static __initdata struct tegra_pingroup_config apalis_t30_pinmux[] = {
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK1_REQ, HDA, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK3_OUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(CLK3_REQ, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(DAP1_DIN, HDA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT, HDA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS, HDA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK, HDA, NORMAL, NORMAL, INPUT),
+
+//multiplexed CAN1/2_RX/TX
+	DEFAULT_PINMUX(DAP2_DIN, RSVD2, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, RSVD2, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS, RSVD2, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, RSVD2, NORMAL, TRISTATE, OUTPUT),
+
+	DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(DAP4_DIN, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(DAP4_DOUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(DAP4_FS, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(DAP4_SCLK, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	I2C_PINMUX(GEN2_I2C_SCL, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(GMI_AD0, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD2, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD3, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD4, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD5, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD6, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD7, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD8, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD9, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD10, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD11, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD12, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD13, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD14, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_AD15, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_ADV_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CLK, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS0_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS1_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS3_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS4_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS6_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_CS7_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_DQS, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(GMI_OE_N, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_RST_N, RSVD3, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(GMI_WAIT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_WP_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GMI_WR_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(GPIO_PU0, GMI, PULL_DOWN, NORMAL, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GPIO_PU1, GMI, PULL_DOWN, NORMAL, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(GPIO_PU2, GMI, PULL_DOWN, NORMAL, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(GPIO_PU3, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+//multiplexed OWR
+	DEFAULT_PINMUX(KB_COL0, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1, KBC, NORMAL, NORMAL, INPUT),
+
+//multiplexed VI_PCLK, VI_VSYNC and VI_HSYNC
+	DEFAULT_PINMUX(KB_COL2, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_COL3, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_COL4, KBC, NORMAL, TRISTATE, INPUT),
+
+//multiplexed VI_D11
+	DEFAULT_PINMUX(KB_COL5, KBC, NORMAL, NORMAL, INPUT),
+//multiplexed VI_D10
+	DEFAULT_PINMUX(KB_COL6, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7, KBC, NORMAL, NORMAL, INPUT),
+
+//multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
+	DEFAULT_PINMUX(KB_ROW0, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW1, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW2, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW3, RSVD2, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW4, RSVD3, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW5, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
+	DEFAULT_PINMUX(KB_ROW7, KBC, NORMAL, TRISTATE, INPUT),
+
+//multiplexed VI_D0
+	DEFAULT_PINMUX(KB_ROW8, KBC, NORMAL, NORMAL, INPUT),
+//multiplexed VI_D1
+	DEFAULT_PINMUX(KB_ROW9, KBC, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_CS0_N, SPI5, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_CS1_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_DC0, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_M1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_PWR0, DISPLAYB, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(LCD_PWR1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(LCD_PWR2, RSVD, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN, SPI5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, SPI5, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(LCD_WR_N, RSVD, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+//multiplexed KB_COL0
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+
+/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+	DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SPI2_CS0_N, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_MISO, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_MOSI, SPI2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(UART2_CTS_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	DEFAULT_PINMUX(UART2_RTS_N, GMI, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+
+	DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
+
+//disable BKL1_PWM_EN# (e.g. PMIC PWM backlight enable) for now
+	DEFAULT_PINMUX(UART3_CTS_N, RSVD1, PULL_UP, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, PWM0, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, INPUT),
+
+//VI pins are all input level-shifted and multiplexed
+//unused VI pins could disable input drivers
+	VI_PINMUX(VI_D0, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D1, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D2, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D3, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D4, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D5, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D6, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D7, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D8, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D9, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D10, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_D11, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_HSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(VI_MCLK, VI, PULL_DOWN, TRISTATE, OUTPUT),	/* NC */
+	VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	VI_PINMUX(VI_VSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
+};
+
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)	\
+	{					\
+		.gpio_nr	= _gpio,	\
+		.is_input	= _is_input,	\
+		.value		= _value,	\
+	}
+
+static struct gpio_init_pin_info apalis_t30_init_gpio_mode[] = {
+};
+
+static void __init apalis_t30_gpio_init_configure(void)
+{
+	int len;
+	int i;
+	struct gpio_init_pin_info *pins_info;
+
+	len = ARRAY_SIZE(apalis_t30_init_gpio_mode);
+	pins_info = apalis_t30_init_gpio_mode;
+
+	for (i = 0; i < len; ++i) {
+		tegra_gpio_init_configure(pins_info->gpio_nr,
+					  pins_info->is_input,
+					  pins_info->value);
+		pins_info++;
+	}
+}
+
+int __init apalis_t30_pinmux_init(void)
+{
+	apalis_t30_gpio_init_configure();
+
+	tegra_pinmux_config_table(apalis_t30_pinmux,
+				  ARRAY_SIZE(apalis_t30_pinmux));
+	tegra_drive_pinmux_config_table(apalis_t30_drive_pinmux,
+					ARRAY_SIZE(apalis_t30_drive_pinmux));
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis_t30-power.c b/arch/arm/mach-tegra/board-apalis_t30-power.c
new file mode 100644
index 000000000000..0344828f031a
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30-power.c
@@ -0,0 +1,510 @@
+/*
+ * arch/arm/mach-tegra/board-apalis_t30-power.c
+ *
+ * Copyright (C) 2013 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mfd/tps6591x.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/tps62360.h>
+#include <linux/regulator/tps6591x-regulator.h>
+#include <linux/resource.h>
+
+#include <mach/edp.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+
+#include "board-apalis_t30.h"
+#include "board.h"
+#include "gpio-names.h"
+#include "tegra3_tsensor.h"
+#include "pm.h"
+#include "wakeups.h"
+#include "wakeups-t3.h"
+
+#define PMC_CTRL		0x0
+#define PMC_CTRL_INTR_LOW	(1 << 17)
+
+/* SW1: +V1.35_VDDIO_DDR */
+static struct regulator_consumer_supply tps6591x_vdd1_supply_0[] = {
+	REGULATOR_SUPPLY("mem_vddio_ddr", NULL),
+	REGULATOR_SUPPLY("t30_vddio_ddr", NULL),
+};
+
+/* SW2: +V1.05 */
+static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = {
+	REGULATOR_SUPPLY("avdd_sata", NULL),
+	REGULATOR_SUPPLY("vdd_sata", NULL),
+	REGULATOR_SUPPLY("avdd_sata_pll", NULL),
+};
+
+/* SW CTRL: +V1.0_VDD_CPU */
+static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = {
+	REGULATOR_SUPPLY("vdd_cpu_pmu", NULL),
+	REGULATOR_SUPPLY("vdd_cpu", NULL),
+//!=vddio_sys!
+	REGULATOR_SUPPLY("vdd_sys", NULL),
+};
+
+/* SWIO: +V1.8 */
+static struct regulator_consumer_supply tps6591x_vio_supply_0[] = {
+	REGULATOR_SUPPLY("vdd_gen1v8", NULL),
+	REGULATOR_SUPPLY("avdd_usb_pll", NULL),
+	REGULATOR_SUPPLY("avdd_osc", NULL),
+	REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+	REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+	REGULATOR_SUPPLY("vdd1v8_satelite", NULL),
+	REGULATOR_SUPPLY("vddio_vi", NULL),
+	REGULATOR_SUPPLY("pwrdet_vi", NULL),
+	REGULATOR_SUPPLY("ldo1", NULL),
+	REGULATOR_SUPPLY("ldo2", NULL),
+	REGULATOR_SUPPLY("ldo6", NULL),
+	REGULATOR_SUPPLY("ldo7", NULL),
+	REGULATOR_SUPPLY("ldo8", NULL),
+	REGULATOR_SUPPLY("vcore_audio", NULL),
+	REGULATOR_SUPPLY("avcore_audio", NULL),
+	REGULATOR_SUPPLY("vcore1_lpddr2", NULL),
+	REGULATOR_SUPPLY("vcom_1v8", NULL),
+	REGULATOR_SUPPLY("pmuio_1v8", NULL),
+	REGULATOR_SUPPLY("avdd_ic_usb", NULL),
+};
+
+/* unused */
+static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = {
+	REGULATOR_SUPPLY("unused_rail_ldo1", NULL),
+};
+
+/* EN_+V3.3 switching via FET: +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
+   see also v3_3 fixed supply */
+//Apalis T30
+//+V3.3_VPP_FUSE
+//POWER_ENABLE_MOCI
+//+V3.3_TOUCH_AVDD_S
+//+V3.3_AUDIO_AVDD_S
+static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = {
+	REGULATOR_SUPPLY("en_V3_3", NULL),
+};
+
+/* +V1.2_CSI */
+static struct regulator_consumer_supply tps6591x_ldo3_supply_0[] = {
+	REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
+	REGULATOR_SUPPLY("pwrdet_mipi", NULL),
+};
+
+/* +V1.2_VDD_RTC */
+static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = {
+	REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+
+/* +V2.8_AVDD_VDAC */
+//only required for analog RGB
+static struct regulator_consumer_supply tps6591x_ldo5_supply_0[] = {
+	REGULATOR_SUPPLY("avdd_vdac", NULL),
+};
+
+//Apalis T30
+/* +V1.05_AVDD_PLLE */
+static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = {
+	REGULATOR_SUPPLY("avdd_plle", NULL),
+};
+
+/* +V1.2_AVDD_PLL */
+static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = {
+	REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
+	REGULATOR_SUPPLY("avdd_pllm", NULL),
+	REGULATOR_SUPPLY("avdd_pllu_d", NULL),
+	REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
+	REGULATOR_SUPPLY("avdd_pllx", NULL),
+};
+
+/* +V1.0_VDD_DDR_HS */
+static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = {
+	REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
+};
+
+#define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \
+	_boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl, _flags) \
+	static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \
+	{								\
+		.regulator = {						\
+			.constraints = {				\
+				.min_uV = (_minmv)*1000,		\
+				.max_uV = (_maxmv)*1000,		\
+				.valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
+						     REGULATOR_MODE_STANDBY), \
+				.valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
+						   REGULATOR_CHANGE_STATUS |  \
+						   REGULATOR_CHANGE_VOLTAGE), \
+				.always_on = _always_on,		\
+				.boot_on = _boot_on,			\
+				.apply_uV = _apply_uv,			\
+			},						\
+			.num_consumer_supplies =			\
+				ARRAY_SIZE(tps6591x_##_name##_supply_##_sname),	\
+			.consumer_supplies = tps6591x_##_name##_supply_##_sname,	\
+			.supply_regulator = _supply_reg,		\
+		},							\
+		.init_uV =  _init_uV * 1000,				\
+		.init_enable = _init_enable,				\
+		.init_apply = _init_apply,				\
+		.ectrl = _ectrl,					\
+		.flags = _flags,					\
+	}
+
+TPS_PDATA_INIT(vdd1, 0,         1350, 1350, 0, 1, 1, 1, -1, 0, 0, 0, 0);
+TPS_PDATA_INIT(vdd2, 0,         1050, 1050, 0, 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0);
+TPS_PDATA_INIT(vddctrl, 0,      800,  1300, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1, 0);
+TPS_PDATA_INIT(vio,  0,         1800, 1800, 0, 1, 1, 0, -1, 0, 0, 0, 0);
+
+TPS_PDATA_INIT(ldo1, 0,         1000, 3300, tps6591x_rails(VIO), 0, 0, 0, -1, 0, 1, 0, 0);
+/* Make sure EN_+V3.3 is always on! */
+TPS_PDATA_INIT(ldo2, 0,         1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 1, 0, 0);
+
+TPS_PDATA_INIT(ldo3, 0,         1200, 1200, 0, 0, 0, 0, -1, 0, 0, 0, 0);
+TPS_PDATA_INIT(ldo4, 0,         900,  1400, 0, 1, 0, 0, -1, 0, 0, 0, LDO_LOW_POWER_ON_SUSPEND);
+TPS_PDATA_INIT(ldo5, 0,         2800, 2800, 0, 0, 0, 0, -1, 0, 0, 0, 0);
+/* AVDD_PLLE should be 1.05V, but ldo_6 can not be adjusted in a 50mV granularity */
+TPS_PDATA_INIT(ldo6, 0,         1000, 1100, tps6591x_rails(VIO), 0, 0, 1, -1, 0, 0, 0, 0);
+
+TPS_PDATA_INIT(ldo7, 0,         1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
+TPS_PDATA_INIT(ldo8, 0,         1000, 1000, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
+
+#if defined(CONFIG_RTC_DRV_TPS6591x)
+static struct tps6591x_rtc_platform_data rtc_data = {
+	.irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM,
+	.time = {
+		.tm_year = 2000,
+		.tm_mon = 0,
+		.tm_mday = 1,
+		.tm_hour = 0,
+		.tm_min = 0,
+		.tm_sec = 0,
+	},
+};
+
+#define TPS_RTC_REG()					\
+	{						\
+		.id	= 0,				\
+		.name	= "rtc_tps6591x",		\
+		.platform_data = &rtc_data,		\
+	}
+#endif
+
+#define TPS_REG(_id, _name, _sname)				\
+	{							\
+		.id	= TPS6591X_ID_##_id,			\
+		.name	= "tps6591x-regulator",			\
+		.platform_data	= &pdata_##_name##_##_sname,	\
+	}
+
+static struct tps6591x_subdev_info apalis_t30_tps_devs[] = {
+	TPS_REG(VDD_1, vdd1, 0),
+	TPS_REG(VDD_2, vdd2, 0),
+	TPS_REG(VDDCTRL, vddctrl, 0),
+	TPS_REG(VIO, vio, 0),
+	TPS_REG(LDO_1, ldo1, 0),
+	TPS_REG(LDO_2, ldo2, 0),
+	TPS_REG(LDO_3, ldo3, 0),
+	TPS_REG(LDO_4, ldo4, 0),
+	TPS_REG(LDO_5, ldo5, 0),
+	TPS_REG(LDO_6, ldo6, 0),
+	TPS_REG(LDO_7, ldo7, 0),
+	TPS_REG(LDO_8, ldo8, 0),
+#if defined(CONFIG_RTC_DRV_TPS6591x)
+	TPS_RTC_REG(),
+#endif
+};
+
+static struct tps6591x_sleep_keepon_data tps_slp_keepon = {
+	.clkout32k_keepon = 1,
+};
+
+static struct tps6591x_platform_data tps_platform = {
+	.irq_base	= TPS6591X_IRQ_BASE,
+	.gpio_base	= TPS6591X_GPIO_BASE,
+	.dev_slp_en	= true,
+	.slp_keepon	= &tps_slp_keepon,
+	.use_power_off	= true,
+};
+
+static struct i2c_board_info __initdata apalis_t30_regulators[] = {
+	{
+		I2C_BOARD_INFO("tps6591x", 0x2D),
+//PWR_INT_IN wake18
+		.irq		= INT_EXTERNAL_PMU,
+		.platform_data	= &tps_platform,
+	},
+};
+
+/* TPS62362 DC-DC converter
+   SW: +V1.2_VDD_CORE */
+static struct regulator_consumer_supply tps6236x_dcdc_supply[] = {
+	REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct tps62360_regulator_platform_data tps6236x_pdata = {
+	.reg_init_data = {					\
+		.constraints = {				\
+			.min_uV =  900000,			\
+			.max_uV = 1400000,			\
+			.valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
+					     REGULATOR_MODE_STANDBY), \
+			.valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
+					   REGULATOR_CHANGE_STATUS |  \
+					   REGULATOR_CHANGE_VOLTAGE), \
+			.always_on = 1,				\
+			.boot_on =  1,				\
+			.apply_uV = 0,				\
+		},						\
+		.num_consumer_supplies = ARRAY_SIZE(tps6236x_dcdc_supply), \
+		.consumer_supplies = tps6236x_dcdc_supply,	\
+		},						\
+	.en_discharge = true,					\
+	.vsel0_gpio = -1,					\
+	.vsel1_gpio = -1,					\
+	.vsel0_def_state = 1,					\
+	.vsel1_def_state = 1,					\
+};
+
+static struct i2c_board_info __initdata tps6236x_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("tps62360", 0x60),
+		.platform_data	= &tps6236x_pdata,
+	},
+};
+
+/* Macro for defining fixed regulator sub device data */
+#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
+#define FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on,		\
+		_boot_on, _gpio_nr, _active_high, _boot_state,		\
+		_millivolts, _od_state)					\
+	static struct regulator_init_data ri_data_##_var =		\
+	{								\
+		.supply_regulator = _in_supply,				\
+		.num_consumer_supplies =				\
+			ARRAY_SIZE(fixed_reg_##_name##_supply),		\
+		.consumer_supplies = fixed_reg_##_name##_supply,	\
+		.constraints = {					\
+			.valid_modes_mask = (REGULATOR_MODE_NORMAL),	\
+			.valid_ops_mask = (REGULATOR_CHANGE_STATUS),	\
+			.always_on = _always_on,			\
+			.boot_on = _boot_on,				\
+		},							\
+	};								\
+	static struct fixed_voltage_config fixed_reg_##_var##_pdata =	\
+	{								\
+		.supply_name = FIXED_SUPPLY(_name),			\
+		.microvolts = _millivolts * 1000,			\
+		.gpio = _gpio_nr,					\
+		.enable_high = _active_high,				\
+		.enabled_at_boot = _boot_state,				\
+		.init_data = &ri_data_##_var,				\
+		.gpio_is_open_drain = _od_state,			\
+	};								\
+	static struct platform_device fixed_reg_##_var##_dev = {	\
+		.name   = "reg-fixed-voltage",				\
+		.id     = _id,						\
+		.dev    = {						\
+			.platform_data = &fixed_reg_##_var##_pdata,	\
+		},							\
+	}
+
+#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on,	\
+		 _gpio_nr, _active_high, _boot_state, _millivolts)	\
+	FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, _boot_on,  \
+		_gpio_nr, _active_high, _boot_state, _millivolts, false)
+
+#define ADD_FIXED_REG(_name)	(&fixed_reg_##_name##_dev)
+
+/* PMU GP6: EN_VDD_HDMI switching via FET: +V1.8_AVDD_HDMI_PLL and +V3.3_AVDD_HDMI */
+static struct regulator_consumer_supply fixed_reg_en_hdmi_supply[] = {
+	REGULATOR_SUPPLY("avdd_hdmi", NULL),
+	REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
+//	REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL),
+//	REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
+};
+
+//EN_VDD_CORE PMIC GPIO2
+//EN_VDD_FUSE PMIC GPIO4
+//EN_VDD_HDMI PMIC GPIO6
+
+FIXED_REG(2, en_hdmi, en_hdmi, NULL, 0, 0, TPS6591X_GPIO_6, true, 1, 1800);
+
+/* +V3.3 is switched on by LDO2, As this can not be modeled we use a fixed
+   regulator without enable, 3.3V must not be switched off anyway.
++V3.3:
+VDD_DDR_RX
+VDDIO_LCD_1
+VDDIO_LCD_2
+VDDIO_CAM
+LM95245
+VDDIO_SYS_01
+VDDIO_SYS_02
+VDDIO_BB
+VDDIO_AUDIO
+VDDIO_GMI_1
+VDDIO_GMI_2
+VDDIO_GMI_3
+VDDIO_UART
+VDDIO_SDMMC1
+AVDD_USB
+VDDIO_SDMMC3
+74AVCAH164245
+VDDIO_PEX_CTL
+TPS65911 VDDIO
+MT29F16G08
+SGTL5000 VDDIO
+STMPE811
+AX88772B VCC3x
+SDIN5D2-2G VCCx  */
+static struct regulator_consumer_supply fixed_reg_v3_3_supply[] = {
+	REGULATOR_SUPPLY("avdd_audio", NULL),
+	REGULATOR_SUPPLY("avdd_usb", NULL),
+	REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
+	REGULATOR_SUPPLY("vddio_sys", NULL),
+	REGULATOR_SUPPLY("vddio_uart", NULL),
+	REGULATOR_SUPPLY("pwrdet_uart", NULL),
+	REGULATOR_SUPPLY("vddio_audio", NULL),
+	REGULATOR_SUPPLY("pwrdet_audio", NULL),
+	REGULATOR_SUPPLY("vddio_bb", NULL),
+	REGULATOR_SUPPLY("pwrdet_bb", NULL),
+	REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
+	REGULATOR_SUPPLY("pwrdet_lcd", NULL),
+	REGULATOR_SUPPLY("vddio_cam", NULL),
+	REGULATOR_SUPPLY("pwrdet_cam", NULL),
+	/* if this supply is defined, the sdhci driver tries
+	 * to set it to 1.8V */
+//	REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.1"),
+	REGULATOR_SUPPLY("pwrdet_sdmmc2", NULL),
+	REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
+	REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
+	REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
+	REGULATOR_SUPPLY("pwrdet_nand", NULL),
+
+	/* SGTL5000 */
+	REGULATOR_SUPPLY("VDDA", "4-000a"),
+	REGULATOR_SUPPLY("VDDIO", "4-000a"),
+
+	REGULATOR_SUPPLY("hvdd_pex", NULL),
+	REGULATOR_SUPPLY("hvdd_sata", NULL),
+};
+
+FIXED_REG(3, v3_3, v3_3, NULL, 1, 1, -1, true, 1, 3300);
+
+/* Gpio switch regulator platform data */
+static struct platform_device *fixed_reg_devs_apalis_t30[] = {
+		ADD_FIXED_REG(en_hdmi),
+		ADD_FIXED_REG(v3_3),
+};
+
+int __init apalis_t30_regulator_init(void)
+{
+	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+	u32 pmc_ctrl;
+
+	/* configure the power management controller to trigger PMU
+	 * interrupts when low */
+
+	pmc_ctrl = readl(pmc + PMC_CTRL);
+	writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+	/* The regulator details have complete constraints */
+	regulator_has_full_constraints();
+
+	tps_platform.num_subdevs =
+			ARRAY_SIZE(apalis_t30_tps_devs);
+	tps_platform.subdevs = apalis_t30_tps_devs;
+
+	i2c_register_board_info(4, apalis_t30_regulators, 1);
+
+	/* Register the TPS6236x. */
+	pr_info("Registering the device TPS62360\n");
+	i2c_register_board_info(4, tps6236x_boardinfo, 1);
+
+	return 0;
+}
+
+int __init apalis_t20_fixed_regulator_init(void)
+{
+	return platform_add_devices(fixed_reg_devs_apalis_t30, ARRAY_SIZE(fixed_reg_devs_apalis_t30));
+}
+subsys_initcall_sync(apalis_t20_fixed_regulator_init);
+
+static void apalis_t30_board_suspend(int lp_state, enum suspend_stage stg)
+{
+	if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
+		tegra_console_uart_suspend();
+}
+
+static void apalis_t30_board_resume(int lp_state, enum resume_stage stg)
+{
+	if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
+		tegra_console_uart_resume();
+}
+
+static struct tegra_suspend_platform_data apalis_t30_suspend_data = {
+	.cpu_timer	= 2000,
+	.cpu_off_timer	= 200,
+	.suspend_mode	= TEGRA_SUSPEND_LP1,
+	.core_timer	= 0x7e7e,
+	.core_off_timer = 0,
+	.corereq_high	= true,
+	.sysclkreq_high	= true,
+	.cpu_lp2_min_residency = 2000,
+	.board_suspend = apalis_t30_board_suspend,
+	.board_resume = apalis_t30_board_resume,
+};
+
+int __init apalis_t30_suspend_init(void)
+{
+	/* Make core_pwr_req to high */
+	apalis_t30_suspend_data.corereq_high = true;
+
+	/* CORE_PWR_REQ to be high required to enable the dc-dc converter tps62361x */
+	apalis_t30_suspend_data.corereq_high = true;
+
+//required?
+	apalis_t30_suspend_data.cpu_timer = 5000;
+	apalis_t30_suspend_data.cpu_off_timer = 5000;
+
+	tegra_init_suspend(&apalis_t30_suspend_data);
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+int __init apalis_t30_edp_init(void)
+{
+	unsigned int regulator_mA;
+
+	regulator_mA = get_maximum_cpu_current_supported();
+	if (!regulator_mA) {
+		regulator_mA = 6000; /* regular T30/s */
+	}
+	pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+
+	tegra_init_cpu_edp_limits(regulator_mA);
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c
new file mode 100644
index 000000000000..5501c75f1eef
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30.c
@@ -0,0 +1,1196 @@
+/*
+ * arch/arm/mach-tegra/board-apalis_t30.c
+ *
+ * Copyright (c) 2013 Toradex, Inc.
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <linux/can/platform/mcp251x.h>
+#include <linux/clk.h>
+#include <linux/types.h> /* required by linux/gpio_keys.h */
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/i2c-tegra.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/leds_pwm.h>
+#include <linux/lm95245.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/spi/spi.h>
+#include <linux/spi-tegra.h>
+#include <linux/tegra_uart.h>
+
+#include <mach/io_dpd.h>
+#include <mach/pci.h>
+#include <mach/sdhci.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <mach/tegra_fiq_debugger.h>
+#include <mach/thermal.h>
+#include <mach/usb_phy.h>
+#include <mach/w1.h>
+
+#include "board-apalis_t30.h"
+#include "board.h"
+#include "clock.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "pm.h"
+
+/* ADC */
+
+//TODO
+
+/* Audio */
+
+/* HDA */
+
+//TODO
+
+/* I2S */
+
+static struct tegra_asoc_platform_data apalis_t30_audio_sgtl5000_pdata = {
+	.gpio_spkr_en		= -1,
+	.gpio_hp_det		= -1,
+	.gpio_hp_mute		= -1,
+	.gpio_int_mic_en	= -1,
+	.gpio_ext_mic_en	= -1,
+	.i2s_param[HIFI_CODEC] = {
+		.audio_port_id	= 2,
+		.i2s_mode	= TEGRA_DAIFMT_I2S,
+		.is_i2s_master	= 1,
+		.sample_size	= 16,
+	},
+	.i2s_param[BASEBAND] = {
+		.audio_port_id	= -1,
+	},
+	.i2s_param[BT_SCO] = {
+		.audio_port_id	= -1,
+	},
+};
+
+static struct platform_device apalis_t30_audio_sgtl5000_device = {
+	.name	= "tegra-snd-colibri_t30-sgtl5000",
+	.id	= 0,
+	.dev = {
+		.platform_data = &apalis_t30_audio_sgtl5000_pdata,
+	},
+};
+
+#ifdef CONFIG_TEGRA_CAMERA
+/* Camera */
+static struct platform_device tegra_camera = {
+	.name	= "tegra_camera",
+	.id	= -1,
+};
+#endif /* CONFIG_TEGRA_CAMERA */
+
+/* CAN */
+
+#if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE)
+static struct mcp251x_platform_data can_pdata = {
+	.oscillator_frequency	= 16000000,
+	.power_enable		= NULL,
+	.transceiver_enable	= NULL
+};
+
+static struct spi_board_info can_board_info[] = {
+	{
+		.bus_num	= 1,		/* SPI2: CAN1 */
+		.chip_select	= 0,
+		.max_speed_hz	= 10000000,
+		.modalias	= "mcp2515",
+		.platform_data	= &can_pdata,
+	},
+	{
+		.bus_num	= 3,		/* SPI4: CAN2 */
+		.chip_select	= 1,
+		.max_speed_hz	= 10000000,
+		.modalias	= "mcp2515",
+		.platform_data	= &can_pdata,
+	},
+};
+
+static void __init apalis_t20_mcp2515_can_init(void)
+{
+	can_board_info[0].irq = gpio_to_irq(CAN1_INT);
+	can_board_info[1].irq = gpio_to_irq(CAN2_INT);
+	spi_register_board_info(can_board_info, ARRAY_SIZE(can_board_info));
+}
+#else /* CONFIG_CAN_MCP251X | CONFIG_CAN_MCP251X_MODULE */
+#define apalis_t20_mcp2515_can_init() do {} while (0)
+#endif /* CONFIG_CAN_MCP251X | CONFIG_CAN_MCP251X_MODULE */
+
+/* CEC */
+
+//TODO
+
+/* Clocks */
+static struct tegra_clk_init_table apalis_t30_clk_init_table[] __initdata = {
+	/* name		parent		rate		enabled */
+	{"audio1",	"i2s1_sync",	0,		false},
+	{"audio2",	"i2s2_sync",	0,		false},
+	{"audio3",	"i2s3_sync",	0,		false},
+	{"blink",	"clk_32k",	32768,		true},
+	{"d_audio",	"clk_m",	12000000,	false},
+	{"dam0",	"clk_m",	12000000,	false},
+	{"dam1",	"clk_m",	12000000,	false},
+	{"dam2",	"clk_m",	12000000,	false},
+
+//required?
+	{"hda",	"pll_p",	108000000,	false},
+	{"hda2codec_2x","pll_p",	48000000,	false},
+
+	{"i2c1",	"pll_p",	3200000,	false},
+	{"i2c2",	"pll_p",	3200000,	false},
+	{"i2c3",	"pll_p",	3200000,	false},
+	{"i2c4",	"pll_p",	3200000,	false},
+	{"i2c5",	"pll_p",	3200000,	false},
+	{"i2s0",	"pll_a_out0",	0,		false},
+	{"i2s1",	"pll_a_out0",	0,		false},
+	{"i2s2",	"pll_a_out0",	0,		false},
+	{"i2s3",	"pll_a_out0",	0,		false},
+	{"pll_m",	NULL,		0,		false},
+	{"pwm",		"pll_p",	3187500,	false},
+	{"spdif_out",	"pll_a_out0",	0,		false},
+	{"vi",		"pll_p",	0,		false},
+	{"vi_sensor",	"pll_p",	150000000,	false},
+	{NULL,		NULL,		0,		0},
+};
+
+/* GPIO */
+
+//TODO: sysfs GPIO exports
+
+/* I2C */
+
+/* Make sure that the pinmuxing enable the 'open drain' feature for pins used
+   for I2C */
+
+/* GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier board) */
+static struct i2c_board_info apalis_t30_i2c_bus1_board_info[] __initdata = {
+	{
+		/* M41T0M6 real time clock on Iris carrier board */
+		I2C_BOARD_INFO("rtc-ds1307", 0x68),
+			.type = "m41t00",
+	},
+};
+
+static struct tegra_i2c_platform_data apalis_t30_i2c1_platform_data = {
+	.adapter_nr	= 0,
+	.arb_recovery	= arb_lost_recovery,
+	.bus_clk_rate	= {400000, 0},
+	.bus_count	= 1,
+	.scl_gpio	= {I2C1_SCL, 0},
+	.sda_gpio	= {I2C1_SDA, 0},
+	.slave_addr	= 0x00FC,
+};
+
+/* GEN2_I2C: unused */
+
+/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
+static struct tegra_i2c_platform_data apalis_t30_i2c4_platform_data = {
+	.adapter_nr	= 3,
+	.arb_recovery	= arb_lost_recovery,
+	.bus_clk_rate	= {10000, 10000},
+	.bus_count	= 1,
+	.scl_gpio	= {I2C2_SCL, 0},
+	.sda_gpio	= {I2C2_SDA, 0},
+	.slave_addr	= 0x00FC,
+};
+
+/* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on carrier
+   board) */
+static struct tegra_i2c_platform_data apalis_t30_i2c3_platform_data = {
+	.adapter_nr	= 2,
+	.arb_recovery	= arb_lost_recovery,
+	.bus_clk_rate	= {400000, 0},
+	.bus_count	= 1,
+	.scl_gpio	= {I2C3_SCL, 0},
+	.sda_gpio	= {I2C3_SDA, 0},
+	.slave_addr	= 0x00FC,
+};
+
+/* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and touch screen
+	    controller */
+
+/* STMPE811 touch screen controller */
+static struct stmpe_ts_platform_data stmpe811_ts_data = {
+	.adc_freq		= 1, /* 3.25 MHz ADC clock speed */
+	.ave_ctrl		= 3, /* 8 sample average control */
+	.fraction_z		= 7, /* 7 length fractional part in z */
+	.i_drive		= 1, /* 50 mA typical 80 mA max touchscreen drivers current limit value */
+	.mod_12b		= 1, /* 12-bit ADC */
+	.ref_sel		= 0, /* internal ADC reference */
+	.sample_time		= 4, /* ADC converstion time: 80 clocks */
+	.settling		= 3, /* 1 ms panel driver settling time */
+	.touch_det_delay	= 5, /* 5 ms touch detect interrupt delay */
+};
+
+static struct stmpe_platform_data stmpe811_data = {
+	.blocks		= STMPE_BLOCK_TOUCHSCREEN,
+	.id		= 1,
+	.irq_base	= STMPE811_IRQ_BASE,
+	.irq_trigger	= IRQF_TRIGGER_FALLING,
+	.ts		= &stmpe811_ts_data,
+};
+
+static void lm95245_probe_callback(struct device *dev);
+
+static struct lm95245_platform_data apalis_t30_lm95245_pdata = {
+	.enable_os_pin	= true,
+	.probe_callback	= lm95245_probe_callback,
+};
+
+static struct i2c_board_info apalis_t30_i2c_bus5_board_info[] __initdata = {
+	{
+		/* SGTL5000 audio codec */
+		I2C_BOARD_INFO("sgtl5000", 0x0a),
+	},
+	{
+		/* STMPE811 touch screen controller */
+		I2C_BOARD_INFO("stmpe", 0x41),
+			.flags = I2C_CLIENT_WAKE,
+			.irq = TEGRA_GPIO_TO_IRQ(TOUCH_PEN_INT),
+			.platform_data = &stmpe811_data,
+			.type = "stmpe811",
+	},
+	{
+		/* LM95245 temperature sensor
+		   Note: OVERT_N directly connected to PMIC PWRDN */
+		I2C_BOARD_INFO("lm95245", 0x4c),
+			.platform_data = &apalis_t30_lm95245_pdata,
+	},
+};
+
+static struct tegra_i2c_platform_data apalis_t30_i2c5_platform_data = {
+	.adapter_nr	= 4,
+	.arb_recovery	= arb_lost_recovery,
+	.bus_clk_rate	= {400000, 0},
+	.bus_count	= 1,
+	.scl_gpio	= {PWR_I2C_SCL, 0},
+	.sda_gpio	= {PWR_I2C_SDA, 0},
+};
+
+static void __init apalis_t30_i2c_init(void)
+{
+	tegra_i2c_device1.dev.platform_data = &apalis_t30_i2c1_platform_data;
+	tegra_i2c_device3.dev.platform_data = &apalis_t30_i2c3_platform_data;
+	tegra_i2c_device4.dev.platform_data = &apalis_t30_i2c4_platform_data;
+	tegra_i2c_device5.dev.platform_data = &apalis_t30_i2c5_platform_data;
+
+	platform_device_register(&tegra_i2c_device1);
+	platform_device_register(&tegra_i2c_device3);
+	platform_device_register(&tegra_i2c_device4);
+	platform_device_register(&tegra_i2c_device5);
+
+	i2c_register_board_info(0, apalis_t30_i2c_bus1_board_info, ARRAY_SIZE(apalis_t30_i2c_bus1_board_info));
+
+	/* enable touch interrupt GPIO */
+	gpio_request(TOUCH_PEN_INT, "TOUCH_PEN_INT");
+	gpio_direction_input(TOUCH_PEN_INT);
+
+	i2c_register_board_info(4, apalis_t30_i2c_bus5_board_info, ARRAY_SIZE(apalis_t30_i2c_bus5_board_info));
+}
+
+/* IrDA */
+
+//TODO
+
+/* Keys */
+
+//TODO
+
+/* MMC/SD */
+
+static struct tegra_sdhci_platform_data apalis_t30_emmc_platform_data = {
+	.cd_gpio	= -1,
+	.ddr_clk_limit	= 52000000,
+	.is_8bit	= 1,
+	.mmc_data = {
+		.built_in = 1,
+	},
+	.power_gpio	= -1,
+	.tap_delay	= 0x0f,
+	.wp_gpio	= -1,
+};
+
+static struct tegra_sdhci_platform_data apalis_t30_mmccard_platform_data = {
+//GPIO tested with GPIOConfig but interrupt not working
+//even 8-bit cards work if plugged during boot
+	.cd_gpio	= MMC1_CD_N,
+	.ddr_clk_limit	= 52000000,
+	.is_8bit	= 1,
+	.power_gpio	= -1,
+	.tap_delay	= 0x0f,
+	.wp_gpio	= -1,
+};
+
+static struct tegra_sdhci_platform_data apalis_t30_sdcard_platform_data = {
+	.cd_gpio	= SD1_CD_N,
+	.ddr_clk_limit	= 52000000,
+	.is_8bit	= 0,
+	.power_gpio	= -1,
+	.tap_delay	= 0x0f,
+	.wp_gpio	= -1,
+};
+
+static void __init apalis_t30_sdhci_init(void)
+{
+	/* register eMMC first */
+	tegra_sdhci_device4.dev.platform_data =
+			&apalis_t30_emmc_platform_data;
+	platform_device_register(&tegra_sdhci_device4);
+
+	tegra_sdhci_device3.dev.platform_data =
+			&apalis_t30_mmccard_platform_data;
+	platform_device_register(&tegra_sdhci_device3);
+
+	tegra_sdhci_device1.dev.platform_data =
+			&apalis_t30_sdcard_platform_data;
+	platform_device_register(&tegra_sdhci_device1);
+}
+
+/* PCIe */
+
+static struct tegra_pci_platform_data apalis_t30_pci_platform_data = {
+	.port_status[0]		= 1,
+	.port_status[1]		= 1,
+	.port_status[2]		= 1,
+	.use_dock_detect	= 0,
+	.gpio			= 0,
+};
+
+static void apalis_t30_pci_init(void)
+{
+	tegra_pci_device.dev.platform_data = &apalis_t30_pci_platform_data;
+	platform_device_register(&tegra_pci_device);
+}
+
+/* PWM LEDs */
+static struct led_pwm tegra_leds_pwm[] = {
+	{
+		.name		= "PWM3",
+		.pwm_id		= 1,
+		.max_brightness	= 255,
+		.pwm_period_ns	= 19600,
+	},
+	{
+		.name		= "PWM2",
+		.pwm_id		= 2,
+		.max_brightness	= 255,
+		.pwm_period_ns	= 19600,
+	},
+	{
+		.name		= "PWM1",
+		.pwm_id		= 3,
+		.max_brightness	= 255,
+		.pwm_period_ns	= 19600,
+	},
+};
+
+static struct led_pwm_platform_data tegra_leds_pwm_data = {
+	.num_leds	= ARRAY_SIZE(tegra_leds_pwm),
+	.leds		= tegra_leds_pwm,
+};
+
+static struct platform_device tegra_led_pwm_device = {
+	.name	= "leds_pwm",
+	.id	= -1,
+	.dev = {
+		.platform_data = &tegra_leds_pwm_data,
+	},
+};
+
+/* RTC */
+
+#ifdef CONFIG_RTC_DRV_TEGRA
+static struct resource tegra_rtc_resources[] = {
+	[0] = {
+		.start	= TEGRA_RTC_BASE,
+		.end	= TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= INT_RTC,
+		.end	= INT_RTC,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device tegra_rtc_device = {
+	.name		= "tegra_rtc",
+	.id		= -1,
+	.resource	= tegra_rtc_resources,
+	.num_resources	= ARRAY_SIZE(tegra_rtc_resources),
+};
+#endif /* CONFIG_RTC_DRV_TEGRA */
+
+/* SATA */
+
+static struct gpio_led apalis_gpio_leds[] = {
+	[0] = {
+		.name                   = "SATA1_ACT_N",
+		.default_trigger        = "ide-disk",
+		.gpio                   = SATA1_ACT_N,
+		.active_low             = 1,
+		.retain_state_suspended = 0,
+	},
+};
+
+static struct gpio_led_platform_data apalis_gpio_led_data = {
+	.num_leds	= ARRAY_SIZE(apalis_gpio_leds),
+	.leds		= apalis_gpio_leds,
+};
+
+static struct platform_device apalis_led_gpio_device = {
+	.name = "leds-gpio",
+	.dev = {
+		.platform_data = &apalis_gpio_led_data,
+	},
+};
+
+#ifdef CONFIG_SATA_AHCI_TEGRA
+static void apalis_t30_sata_init(void)
+{
+	platform_device_register(&tegra_sata_device);
+	platform_device_register(&apalis_led_gpio_device);
+}
+#else
+static void apalis_t30_sata_init(void) { }
+#endif
+
+/* SPI */
+
+#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
+static struct spi_board_info tegra_spi_devices[] __initdata = {
+	{
+		.bus_num	= 0,		/* SPI1: Apalis SPI1 */
+		.chip_select	= 0,
+		.irq		= 0,
+		.max_speed_hz	= 50000000,
+		.modalias	= "spidev",
+		.mode		= SPI_MODE_0,
+		.platform_data	= NULL,
+	},
+	{
+		.bus_num	= 4,		/* SPI5: Apalis SPI2 */
+		.chip_select	= 2,
+		.irq		= 0,
+		.max_speed_hz	= 50000000,
+		.modalias	= "spidev",
+		.mode		= SPI_MODE_0,
+		.platform_data	= NULL,
+	},
+};
+
+static void __init apalis_t30_register_spidev(void)
+{
+	spi_register_board_info(tegra_spi_devices,
+				ARRAY_SIZE(tegra_spi_devices));
+}
+#else /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */
+#define apalis_t30_register_spidev() do {} while (0)
+#endif /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */
+
+static struct platform_device *apalis_t30_spi_devices[] __initdata = {
+	&tegra_spi_device1,
+	&tegra_spi_device2,
+	&tegra_spi_device4,
+	&tegra_spi_device5,
+};
+
+static struct spi_clk_parent spi_parent_clk[] = {
+	[0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+	[1] = {.name = "pll_m"},
+	[2] = {.name = "clk_m"},
+#else /* !CONFIG_TEGRA_PLLM_RESTRICTED */
+	[1] = {.name = "clk_m"},
+#endif /* !CONFIG_TEGRA_PLLM_RESTRICTED */
+};
+
+static struct tegra_spi_platform_data apalis_t30_spi_pdata = {
+	.is_dma_based		= true,
+	.max_dma_buffer		= 16 * 1024,
+	.is_clkon_always	= false,
+	.max_rate		= 100000000,
+};
+
+static void __init apalis_t30_spi_init(void)
+{
+	int i;
+	struct clk *c;
+
+	for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
+		c = tegra_get_clock_by_name(spi_parent_clk[i].name);
+		if (IS_ERR_OR_NULL(c)) {
+			pr_err("Not able to get the clock for %s\n",
+						spi_parent_clk[i].name);
+			continue;
+		}
+		spi_parent_clk[i].parent_clk = c;
+		spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+	}
+	apalis_t30_spi_pdata.parent_clk_list = spi_parent_clk;
+	apalis_t30_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
+	tegra_spi_device1.dev.platform_data = &apalis_t30_spi_pdata;
+	platform_add_devices(apalis_t30_spi_devices,
+				ARRAY_SIZE(apalis_t30_spi_devices));
+}
+
+/* Thermal throttling */
+
+static void *apalis_t30_alert_data;
+static void (*apalis_t30_alert_func)(void *);
+static int apalis_t30_low_edge = 0;
+static int apalis_t30_low_hysteresis = 3000;
+static int apalis_t30_low_limit = 0;
+static struct device *lm95245_device = NULL;
+static int thermd_alert_irq_disabled = 0;
+struct work_struct thermd_alert_work;
+struct workqueue_struct *thermd_alert_workqueue;
+
+static struct balanced_throttle throttle_list[] = {
+#ifdef CONFIG_TEGRA_THERMAL_THROTTLE
+	{
+		.id = BALANCED_THROTTLE_ID_TJ,
+		.throt_tab_size = 10,
+		.throt_tab = {
+			{      0, 1000 },
+			{ 640000, 1000 },
+			{ 640000, 1000 },
+			{ 640000, 1000 },
+			{ 640000, 1000 },
+			{ 640000, 1000 },
+			{ 760000, 1000 },
+			{ 760000, 1050 },
+			{1000000, 1050 },
+			{1000000, 1100 },
+		},
+	},
+#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+	{
+		.id = BALANCED_THROTTLE_ID_SKIN,
+		.throt_tab_size = 6,
+		.throt_tab = {
+			{ 640000, 1200 },
+			{ 640000, 1200 },
+			{ 760000, 1200 },
+			{ 760000, 1200 },
+			{1000000, 1200 },
+			{1000000, 1200 },
+		},
+	},
+#endif /* CONFIG_TEGRA_SKIN_THROTTLE */
+};
+
+/* All units are in millicelsius */
+static struct tegra_thermal_data thermal_data = {
+	.shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
+	.temp_shutdown = 115000,
+
+#if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
+	.throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
+#endif
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+	.edp_offset = TDIODE_OFFSET, /* edp based on tdiode */
+	.hysteresis_edp = 3000,
+#endif
+#ifdef CONFIG_TEGRA_THERMAL_THROTTLE
+	.temp_throttle = 85000,
+	.tc1 = 0,
+	.tc2 = 1,
+	.passive_delay = 2000,
+#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+	.skin_device_id = THERMAL_DEVICE_ID_SKIN,
+	.temp_throttle_skin = 43000,
+	.tc1_skin = 0,
+	.tc2_skin = 1,
+	.passive_delay_skin = 5000,
+
+	.skin_temp_offset = 9793,
+	.skin_period = 1100,
+	.skin_devs_size = 2,
+	.skin_devs = {
+		{
+			THERMAL_DEVICE_ID_NCT_EXT,
+			{
+				2, 1, 1, 1,
+				1, 1, 1, 1,
+				1, 1, 1, 0,
+				1, 1, 0, 0,
+				0, 0, -1, -7
+			}
+		},
+		{
+			THERMAL_DEVICE_ID_NCT_INT,
+			{
+				-11, -7, -5, -3,
+				-3, -2, -1, 0,
+				0, 0, 1, 1,
+				1, 2, 2, 3,
+				4, 6, 11, 18
+			}
+		},
+	},
+#endif /* CONFIG_TEGRA_SKIN_THROTTLE */
+};
+
+/* Over-temperature shutdown OS aka high limit GPIO pin interrupt handler */
+static irqreturn_t thermd_alert_irq(int irq, void *data)
+{
+	disable_irq_nosync(irq);
+	thermd_alert_irq_disabled = 1;
+	queue_work(thermd_alert_workqueue, &thermd_alert_work);
+
+	return IRQ_HANDLED;
+}
+
+/* Gets both entered by THERMD_ALERT GPIO interrupt as well as re-scheduled. */
+static void thermd_alert_work_func(struct work_struct *work)
+{
+	int temp = 0;
+
+	lm95245_get_remote_temp(lm95245_device, &temp);
+
+	/* This emulates NCT1008 low limit behaviour */
+	if (!apalis_t30_low_edge && temp <= apalis_t30_low_limit) {
+		apalis_t30_alert_func(apalis_t30_alert_data);
+		apalis_t30_low_edge = 1;
+	} else if (apalis_t30_low_edge && temp > apalis_t30_low_limit + apalis_t30_low_hysteresis) {
+		apalis_t30_low_edge = 0;
+	}
+
+	/* Avoid unbalanced enable for IRQ 367 */
+	if (thermd_alert_irq_disabled) {
+		apalis_t30_alert_func(apalis_t30_alert_data);
+		thermd_alert_irq_disabled = 0;
+		enable_irq(TEGRA_GPIO_TO_IRQ(THERMD_ALERT_N));
+	}
+
+	/* Keep re-scheduling */
+	msleep(2000);
+	queue_work(thermd_alert_workqueue, &thermd_alert_work);
+}
+
+static int lm95245_get_temp(void *_data, long *temp)
+{
+	struct device *lm95245_device = _data;
+	int lm95245_temp = 0;
+	lm95245_get_remote_temp(lm95245_device, &lm95245_temp);
+	*temp = lm95245_temp;
+	return 0;
+}
+
+static int lm95245_get_temp_low(void *_data, long *temp)
+{
+	*temp = 0;
+	return 0;
+}
+
+/* Our temperature sensor only allows triggering an interrupt on over-
+   temperature shutdown aka the high limit we therefore need to setup a
+   workqueue to catch leaving the low limit. */
+static int lm95245_set_limits(void *_data,
+			long lo_limit_milli,
+			long hi_limit_milli)
+{
+	struct device *lm95245_device = _data;
+	apalis_t30_low_limit = lo_limit_milli;
+	if (lm95245_device) lm95245_set_remote_os_limit(lm95245_device, hi_limit_milli);
+	return 0;
+}
+
+static int lm95245_set_alert(void *_data,
+				void (*alert_func)(void *),
+				void *alert_data)
+{
+	lm95245_device = _data;
+	apalis_t30_alert_func = alert_func;
+	apalis_t30_alert_data = alert_data;
+	return 0;
+}
+
+static int lm95245_set_shutdown_temp(void *_data, long shutdown_temp)
+{
+	struct device *lm95245_device = _data;
+	if (lm95245_device) lm95245_set_remote_critical_limit(lm95245_device, shutdown_temp);
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+/* Internal aka local board/case temp */
+static int lm95245_get_itemp(void *dev_data, long *temp)
+{
+	struct device *lm95245_device = dev_data;
+	int lm95245_temp = 0;
+	lm95245_get_local_temp(lm95245_device, &lm95245_temp);
+	*temp = lm95245_temp;
+	return 0;
+}
+#endif /* CONFIG_TEGRA_SKIN_THROTTLE */
+
+static void lm95245_probe_callback(struct device *dev)
+{
+	struct tegra_thermal_device *lm95245_remote;
+
+	lm95245_remote = kzalloc(sizeof(struct tegra_thermal_device),
+					GFP_KERNEL);
+	if (!lm95245_remote) {
+		pr_err("unable to allocate thermal device\n");
+		return;
+	}
+
+	lm95245_remote->name = "lm95245_remote";
+	lm95245_remote->id = THERMAL_DEVICE_ID_NCT_EXT;
+	lm95245_remote->data = dev;
+	lm95245_remote->offset = TDIODE_OFFSET;
+	lm95245_remote->get_temp = lm95245_get_temp;
+	lm95245_remote->get_temp_low = lm95245_get_temp_low;
+	lm95245_remote->set_limits = lm95245_set_limits;
+	lm95245_remote->set_alert = lm95245_set_alert;
+	lm95245_remote->set_shutdown_temp = lm95245_set_shutdown_temp;
+
+	tegra_thermal_device_register(lm95245_remote);
+
+#ifdef CONFIG_TEGRA_SKIN_THROTTLE
+	{
+		struct tegra_thermal_device *lm95245_local;
+		lm95245_local = kzalloc(sizeof(struct tegra_thermal_device),
+						GFP_KERNEL);
+		if (!lm95245_local) {
+			kfree(lm95245_local);
+			pr_err("unable to allocate thermal device\n");
+			return;
+		}
+
+		lm95245_local->name = "lm95245_local";
+		lm95245_local->id = THERMAL_DEVICE_ID_NCT_INT;
+		lm95245_local->data = dev;
+		lm95245_local->get_temp = lm95245_get_itemp;
+
+		tegra_thermal_device_register(lm95245_local);
+	}
+#endif /* CONFIG_TEGRA_SKIN_THROTTLE */
+
+	if (request_irq(TEGRA_GPIO_TO_IRQ(THERMD_ALERT_N), thermd_alert_irq,
+			IRQF_TRIGGER_LOW, "THERMD_ALERT_N", NULL))
+		pr_err("%s: unable to register THERMD_ALERT_N interrupt\n", __func__);
+}
+
+static void apalis_t30_thermd_alert_init(void)
+{
+	gpio_request(THERMD_ALERT_N, "THERMD_ALERT_N");
+	gpio_direction_input(THERMD_ALERT_N);
+
+	thermd_alert_workqueue = create_singlethread_workqueue("THERMD_ALERT_N");
+
+	INIT_WORK(&thermd_alert_work, thermd_alert_work_func);
+}
+
+/* UART */
+
+static struct platform_device *apalis_t30_uart_devices[] __initdata = {
+	&tegra_uarta_device, /* Apalis UART1 */
+	&tegra_uartd_device, /* Apalis UART2 */
+	&tegra_uartb_device, /* Apalis UART3 */
+	&tegra_uartc_device, /* Apalis UART4 */
+};
+
+static struct uart_clk_parent uart_parent_clk[] = {
+	[0] = {.name = "clk_m"},
+	[1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+	[2] = {.name = "pll_m"},
+#endif
+};
+
+static struct tegra_uart_platform_data apalis_t30_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+	int debug_port_id;
+
+	debug_port_id = get_tegra_uart_debug_port_id();
+	if (debug_port_id < 0) {
+		debug_port_id = 0;
+	}
+
+	switch (debug_port_id) {
+	case 0:
+		/* UARTA is the debug port. */
+		pr_info("Selecting UARTA as the debug console\n");
+		apalis_t30_uart_devices[0] = &debug_uarta_device;
+		debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+		debug_uart_port_base = ((struct plat_serial8250_port *)(
+			debug_uarta_device.dev.platform_data))->mapbase;
+		break;
+
+	case 1:
+		/* UARTB is the debug port. */
+		pr_info("Selecting UARTB as the debug console\n");
+		apalis_t30_uart_devices[2] = &debug_uartb_device;
+		debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
+		debug_uart_port_base = ((struct plat_serial8250_port *)(
+			debug_uartb_device.dev.platform_data))->mapbase;
+		break;
+
+	case 2:
+		/* UARTC is the debug port. */
+		pr_info("Selecting UARTC as the debug console\n");
+		apalis_t30_uart_devices[3] = &debug_uartc_device;
+		debug_uart_clk = clk_get_sys("serial8250.0", "uartc");
+		debug_uart_port_base = ((struct plat_serial8250_port *)(
+			debug_uartb_device.dev.platform_data))->mapbase;
+		break;
+
+	case 3:
+		/* UARTD is the debug port. */
+		pr_info("Selecting UARTD as the debug console\n");
+		apalis_t30_uart_devices[1] = &debug_uartd_device;
+		debug_uart_clk = clk_get_sys("serial8250.0", "uartd");
+		debug_uart_port_base = ((struct plat_serial8250_port *)(
+			debug_uartd_device.dev.platform_data))->mapbase;
+		break;
+
+	default:
+		pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
+		apalis_t30_uart_devices[0] = &debug_uarta_device;
+		debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+		debug_uart_port_base = ((struct plat_serial8250_port *)(
+			debug_uarta_device.dev.platform_data))->mapbase;
+		break;
+	}
+	return;
+}
+
+static void __init apalis_t30_uart_init(void)
+{
+	struct clk *c;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+		c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+		if (IS_ERR_OR_NULL(c)) {
+			pr_err("Not able to get the clock for %s\n",
+						uart_parent_clk[i].name);
+			continue;
+		}
+		uart_parent_clk[i].parent_clk = c;
+		uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+	}
+	apalis_t30_uart_pdata.parent_clk_list = uart_parent_clk;
+	apalis_t30_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+	tegra_uarta_device.dev.platform_data = &apalis_t30_uart_pdata;
+	tegra_uartb_device.dev.platform_data = &apalis_t30_uart_pdata;
+	tegra_uartc_device.dev.platform_data = &apalis_t30_uart_pdata;
+	tegra_uartd_device.dev.platform_data = &apalis_t30_uart_pdata;
+
+	/* Register low speed only if it is selected */
+	if (!is_tegra_debug_uartport_hs()) {
+		uart_debug_init();
+		/* Clock enable for the debug channel */
+		if (!IS_ERR_OR_NULL(debug_uart_clk)) {
+			pr_info("The debug console clock name is %s\n",
+						debug_uart_clk->name);
+			c = tegra_get_clock_by_name("pll_p");
+			if (IS_ERR_OR_NULL(c))
+				pr_err("Not getting the parent clock pll_p\n");
+			else
+				clk_set_parent(debug_uart_clk, c);
+
+			clk_enable(debug_uart_clk);
+			clk_set_rate(debug_uart_clk, clk_get_rate(c));
+		} else {
+			pr_err("Not getting the clock %s for debug console\n",
+					debug_uart_clk->name);
+		}
+	}
+
+	platform_add_devices(apalis_t30_uart_devices,
+				ARRAY_SIZE(apalis_t30_uart_devices));
+}
+
+/* USB */
+
+//TODO: overcurrent
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+	.has_hostpc	= true,
+	.op_mode	= TEGRA_USB_OPMODE_DEVICE,
+	.phy_intf	= TEGRA_USB_PHY_INTF_UTMI,
+	.port_otg	= true,
+	.u_cfg.utmi = {
+		.elastic_limit		= 16,
+		.hssync_start_delay	= 0,
+		.idle_wait_delay	= 17,
+		.term_range_adj		= 6,
+		.xcvr_lsfslew		= 2,
+		.xcvr_lsrslew		= 2,
+		.xcvr_setup		= 8,
+		.xcvr_setup_offset	= 0,
+		.xcvr_use_fuses		= 1,
+	},
+	.u_data.dev = {
+		.charging_supported		= false,
+		.remote_wakeup_supported	= false,
+		.vbus_gpio			= -1,
+		.vbus_pmu_irq			= 0,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+	.has_hostpc	= true,
+	.op_mode	= TEGRA_USB_OPMODE_HOST,
+	.phy_intf	= TEGRA_USB_PHY_INTF_UTMI,
+	.port_otg	= true,
+	.u_cfg.utmi = {
+		.elastic_limit		= 16,
+		.hssync_start_delay	= 0,
+		.idle_wait_delay	= 17,
+		.term_range_adj		= 6,
+		.xcvr_lsfslew		= 2,
+		.xcvr_lsrslew		= 2,
+		.xcvr_setup		= 15,
+		.xcvr_setup_offset	= 0,
+		.xcvr_use_fuses		= 1,
+	},
+	.u_data.host = {
+		.hot_plug			= true,
+		.power_off_on_suspend		= false,
+		.remote_wakeup_supported	= true,
+		.vbus_gpio			= USBO1_EN,
+		.vbus_gpio_inverted		= 0,
+		.vbus_reg			= NULL,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+	.has_hostpc	= true,
+	.op_mode	= TEGRA_USB_OPMODE_HOST,
+	.phy_intf	= TEGRA_USB_PHY_INTF_UTMI,
+	.port_otg	= false,
+	.u_cfg.utmi = {
+		.elastic_limit		= 16,
+		.hssync_start_delay	= 0,
+		.idle_wait_delay	= 17,
+		.term_range_adj		= 6,
+		.xcvr_lsfslew		= 2,
+		.xcvr_lsrslew		= 2,
+		.xcvr_setup		= 15,
+		.xcvr_setup_offset	= 0,
+		.xcvr_use_fuses		= 1,
+	},
+	.u_data.host = {
+		.hot_plug			= true,
+		.power_off_on_suspend		= false,
+		.remote_wakeup_supported	= true,
+		.vbus_gpio			= USBH_EN,
+		.vbus_gpio_inverted		= 0,
+		.vbus_reg			= NULL,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+	.has_hostpc	= true,
+	.op_mode	= TEGRA_USB_OPMODE_HOST,
+	.phy_intf	= TEGRA_USB_PHY_INTF_UTMI,
+	.port_otg	= false,
+	.u_cfg.utmi = {
+		.elastic_limit		= 16,
+		.hssync_start_delay	= 0,
+		.idle_wait_delay	= 17,
+		.term_range_adj		= 6,
+		.xcvr_lsfslew		= 2,
+		.xcvr_lsrslew		= 2,
+		.xcvr_setup		= 8,
+		.xcvr_setup_offset	= 0,
+		.xcvr_use_fuses		= 1,
+	},
+	.u_data.host = {
+		.hot_plug			= true,
+		.power_off_on_suspend		= false,
+		.remote_wakeup_supported	= true,
+		/* Uses same USBH_EN as EHCI2 */
+		.vbus_gpio			= -1,
+		.vbus_gpio_inverted		= 0,
+		.vbus_reg			= NULL,
+	},
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+	.ehci_device = &tegra_ehci1_device,
+	.ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+static void apalis_t30_usb_init(void)
+{
+	/* OTG should be the first to be registered
+	   EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+	tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+	platform_device_register(&tegra_otg_device);
+
+	/* setup the udc platform data */
+	tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+	platform_device_register(&tegra_udc_device);
+
+	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+	tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
+	platform_device_register(&tegra_ehci2_device);
+
+	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
+	tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+	platform_device_register(&tegra_ehci3_device);
+}
+
+/* W1, aka OWR, aka OneWire */
+
+#ifdef CONFIG_W1_MASTER_TEGRA
+struct tegra_w1_timings apalis_t30_w1_timings = {
+		.tsu		= 1,
+		.trelease	= 0xf,
+		.trdv		= 0xf,
+		.tlow0		= 0x3c,
+		.tlow1		= 1,
+		.tslot		= 0x77,
+
+		.tpdl		= 0x78,
+		.tpdh		= 0x1e,
+		.trstl		= 0x1df,
+		.trsth		= 0x1df,
+		.rdsclk		= 0x7,
+		.psclk		= 0x50,
+};
+
+struct tegra_w1_platform_data apalis_t30_w1_platform_data = {
+	.clk_id		= "tegra_w1",
+	.timings	= &apalis_t30_w1_timings,
+};
+#endif /* CONFIG_W1_MASTER_TEGRA */
+
+static struct platform_device *apalis_t30_devices[] __initdata = {
+	&tegra_pmu_device,
+#if defined(CONFIG_RTC_DRV_TEGRA)
+	&tegra_rtc_device,
+#endif
+#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
+	&tegra_smmu_device,
+#endif
+	&tegra_wdt0_device,
+	&tegra_wdt1_device,
+	&tegra_wdt2_device,
+#if defined(CONFIG_TEGRA_AVP)
+	&tegra_avp_device,
+#endif
+#ifdef CONFIG_TEGRA_CAMERA
+	&tegra_camera,
+#endif
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+	&tegra_se_device,
+#endif
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+	&tegra_aes_device,
+#endif
+
+	&tegra_ahub_device,
+	&tegra_dam_device0,
+	&tegra_dam_device1,
+	&tegra_dam_device2,
+	&tegra_i2s_device2,
+	&tegra_spdif_device,
+	&spdif_dit_device,
+	&tegra_pcm_device,
+	&apalis_t30_audio_sgtl5000_device,
+
+	&tegra_cec_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+	&tegra_aes_device,
+#endif
+#ifdef CONFIG_KEYBOARD_GPIO
+//	&apalis_t30_keys_device,
+#endif
+	&tegra_led_pwm_device,
+	&tegra_pwfm1_device,
+	&tegra_pwfm2_device,
+	&tegra_pwfm3_device,
+#ifdef CONFIG_W1_MASTER_TEGRA
+	&tegra_w1_device,
+#endif
+};
+
+static void __init apalis_t30_init(void)
+{
+	tegra_thermal_init(&thermal_data,
+				throttle_list,
+				ARRAY_SIZE(throttle_list));
+	tegra_clk_init_from_table(apalis_t30_clk_init_table);
+	apalis_t30_pinmux_init();
+	apalis_t30_thermd_alert_init();
+	apalis_t30_i2c_init();
+	apalis_t30_spi_init();
+	apalis_t30_usb_init();
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+	apalis_t30_edp_init();
+#endif
+	apalis_t30_uart_init();
+#ifdef CONFIG_W1_MASTER_TEGRA
+	tegra_w1_device.dev.platform_data = &apalis_t30_w1_platform_data;
+#endif
+	platform_add_devices(apalis_t30_devices, ARRAY_SIZE(apalis_t30_devices));
+	tegra_ram_console_debug_init();
+	tegra_io_dpd_init();
+	apalis_t30_sdhci_init();
+	apalis_t30_regulator_init();
+	apalis_t30_suspend_init();
+	apalis_t30_panel_init();
+//	apalis_t30_sensors_init();
+	apalis_t30_sata_init();
+	apalis_t30_emc_init();
+	apalis_t30_register_spidev();
+
+	tegra_release_bootloader_fb();
+	apalis_t30_pci_init();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+	tegra_wdt_recovery_init();
+#endif
+	tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
+	apalis_t20_mcp2515_can_init();
+}
+
+static void __init apalis_t30_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+	/* Support 1920X1080 32bpp,double buffered on HDMI*/
+	tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
+#else
+	tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
+#endif
+	tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+static const char *apalis_t30_dt_board_compat[] = {
+	"toradex,apalis_t30",
+	NULL
+};
+
+MACHINE_START(APALIS_T30, "Toradex Apalis T30")
+	.boot_params	= 0x80000100,
+	.dt_compat	= apalis_t30_dt_board_compat,
+	.init_early	= tegra_init_early,
+	.init_irq	= tegra_init_irq,
+	.init_machine	= apalis_t30_init,
+	.map_io		= tegra_map_common_io,
+	.reserve	= apalis_t30_reserve,
+	.timer		= &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-apalis_t30.h b/arch/arm/mach-tegra/board-apalis_t30.h
new file mode 100644
index 000000000000..38a86f67470c
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis_t30.h
@@ -0,0 +1,141 @@
+/*
+ * arch/arm/mach-tegra/board-apalis_t30.h
+ *
+ * Copyright (c) 2013 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_APALIS_T30_H
+#define _MACH_TEGRA_BOARD_APALIS_T30_H
+
+#include <linux/mfd/tps6591x.h>
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+/* GPIO */
+
+#define BKL1_ON		TEGRA_GPIO_PV2
+#define BKL1_PWM_EN_N	TEGRA_GPIO_PA1
+
+#define CAN1_INT	TEGRA_GPIO_PW2
+#define CAN2_INT	TEGRA_GPIO_PW3
+
+#define GPIO1		TEGRA_GPIO_PS2
+#define GPIO2		TEGRA_GPIO_PS3
+#define GPIO3		TEGRA_GPIO_PS4
+#define GPIO4		TEGRA_GPIO_PS5
+#define GPIO5		TEGRA_GPIO_PS6
+#define GPIO6		TEGRA_GPIO_PQ0
+#define GPIO7		TEGRA_GPIO_PS7
+#define GPIO8		TEGRA_GPIO_PQ1
+
+#define HDMI1_HPD	TEGRA_GPIO_PN7
+
+#define I2C1_SCL	TEGRA_GPIO_PC4
+#define I2C1_SDA	TEGRA_GPIO_PC5
+
+#define I2C2_SCL	TEGRA_GPIO_PV4
+#define I2C2_SDA	TEGRA_GPIO_PV5
+
+#define I2C3_SCL	TEGRA_GPIO_PBB1
+#define I2C3_SDA	TEGRA_GPIO_PBB2
+
+#define LAN_SMB_ALERT_N	TEGRA_GPIO_PZ5
+
+#define LVDS_MODE	TEGRA_GPIO_PBB0
+#define LVDS_6B_8B_N	TEGRA_GPIO_PBB3
+#define LVDS_OE		TEGRA_GPIO_PBB4
+#define LVDS_PDWN_N	TEGRA_GPIO_PBB5
+#define LVDS_R_F_N	TEGRA_GPIO_PBB6
+#define LVDS_MAP	TEGRA_GPIO_PBB7
+#define LVDS_RS		TEGRA_GPIO_PCC1
+#define LVDS_DDR_N	TEGRA_GPIO_PCC2
+
+#define MMC1_CD_N	TEGRA_GPIO_PV3
+
+#define PWR_I2C_SCL	TEGRA_GPIO_PZ6
+#define PWR_I2C_SDA	TEGRA_GPIO_PZ7
+
+#define RESET_MOCI_N	TEGRA_GPIO_PI4
+
+#define SATA1_ACT_N	TEGRA_GPIO_PDD0
+
+#define SD1_CD_N	TEGRA_GPIO_PCC5
+
+#define THERMD_ALERT_N	TEGRA_GPIO_PD2
+
+#define TOUCH_PEN_INT	TEGRA_GPIO_PV0
+
+#define TS1		TEGRA_GPIO_PI1
+#define TS2		TEGRA_GPIO_PQ7
+#define TS3		TEGRA_GPIO_PQ5
+#define TS4		TEGRA_GPIO_PQ6
+#define TS5		TEGRA_GPIO_PS0
+#define TS6		TEGRA_GPIO_PS1
+
+#define USBH_EN		TEGRA_GPIO_PDD1
+#define USBH_OC_N	TEGRA_GPIO_PDD2
+#define USBO1_EN	TEGRA_GPIO_PT5
+#define USBO1_OC_N	TEGRA_GPIO_PT6
+
+#define WAKE1_MICO	TEGRA_GPIO_PV1
+
+/* External peripheral act as gpio */
+/* TPS6591x GPIOs */
+#define TPS6591X_GPIO_BASE	TEGRA_NR_GPIOS
+#define TPS6591X_GPIO_0		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP0)
+#define TPS6591X_GPIO_1		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP1)
+#define TPS6591X_GPIO_2		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP2)
+#define TPS6591X_GPIO_3		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP3)
+#define TPS6591X_GPIO_4		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP4)
+#define TPS6591X_GPIO_5		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP5)
+#define TPS6591X_GPIO_6		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP6)
+#define TPS6591X_GPIO_7		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP7)
+#define TPS6591X_GPIO_8		(TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP8)
+#define TPS6591X_GPIO_END	(TPS6591X_GPIO_BASE + TPS6591X_GPIO_NR)
+
+#define AC_PRESENT_GPIO		TPS6591X_GPIO_4
+
+/*****************Interrupt tables ******************/
+/* External peripheral act as interrupt controller */
+/* TPS6591x IRQs */
+#define TPS6591X_IRQ_BASE	TEGRA_NR_IRQS
+#define TPS6591X_IRQ_END	(TPS6591X_IRQ_BASE + 18)
+
+#define AC_PRESENT_INT		(TPS6591X_INT_GPIO4 + TPS6591X_IRQ_BASE)
+
+/* STMPE811 IRQs */
+#define STMPE811_IRQ_BASE	TPS6591X_IRQ_END
+#define STMPE811_IRQ_END	(STMPE811_IRQ_BASE + 22)
+
+#define TDIODE_OFFSET	(10000)	/* in millicelsius */
+
+/* Run framebuffer in VGA mode */
+#define TEGRA_FB_VGA
+
+int apalis_t30_regulator_init(void);
+int apalis_t30_suspend_init(void);
+int apalis_t30_pinmux_init(void);
+int apalis_t30_panel_init(void);
+int apalis_t30_sensors_init(void);
+int apalis_t30_gpio_switch_regulator_init(void);
+int apalis_t30_pins_state_init(void);
+int apalis_t30_emc_init(void);
+int apalis_t30_power_off_init(void);
+int apalis_t30_edp_init(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 01841f32f4c4..703393ba7bd9 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -25,12 +25,12 @@
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 #define USE_PLL_LOCK_BITS 0	/* Never use lock bits on Tegra2 */
 #else
-#ifdef CONFIG_MACH_COLIBRI_T30
+#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_COLIBRI_T30)
 /* Hack: avoid lock-up during boot-up due to missing pll_a lock bit. */
-#define USE_PLL_LOCK_BITS 0	/* Never use lock bits on Colibri T30 */
-#else /* CONFIG_MACH_COLIBRI_T30 */
+#define USE_PLL_LOCK_BITS 0	/* Never use lock bits on Apalis/Colibri T30 */
+#else /* CONFIG_MACH_APALIS_T30 | CONFIG_MACH_COLIBRI_T30 */
 #define USE_PLL_LOCK_BITS 1	/* Use lock bits for PLL stabilisation */
-#endif /* CONFIG_MACH_COLIBRI_T30 */
+#endif /* CONFIG_MACH_APALIS_T30 | CONFIG_MACH_COLIBRI_T30 */
 #define USE_PLLE_SS 1		/* Use spread spectrum coefficients for PLLE */
 #define PLL_POST_LOCK_DELAY 50	/* Safety delay after lock is detected */
 #endif
diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c
index be9470fa62ac..8fb6a084bc86 100644
--- a/arch/arm/mach-tegra/pm-t3.c
+++ b/arch/arm/mach-tegra/pm-t3.c
@@ -480,7 +480,7 @@ struct tegra_io_dpd tegra_list_io_dpd[] = {
 	/* sd dpd bits in dpd2 register */
 	IO_DPD_INFO("sdhci-tegra.0",	1,	1), /* SDMMC1 */
 	IO_DPD_INFO("sdhci-tegra.2",	1,	2), /* SDMMC3 */
-#ifndef CONFIG_MACH_COLIBRI_T30
+#if !defined(CONFIG_MACH_APALIS_T30) && !defined(CONFIG_MACH_COLIBRI_T30)
 /* Hack: fix eMMC detection */
 	IO_DPD_INFO("sdhci-tegra.3",	1,	3), /* SDMMC4 */
 #endif
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index 468f50dee329..fafa5a22157a 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -844,7 +844,7 @@ static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate)
 	if (c->dvfs) {
 		if (!c->dvfs->dvfs_rail)
 			return -ENOSYS;
-#ifndef CONFIG_MACH_COLIBRI_T30
+#if !defined(CONFIG_MACH_APALIS_T30) && !defined(CONFIG_MACH_COLIBRI_T30)
 /* Hack: avoid extensive warnings being logged during boot-up. */
 		else if ((!c->dvfs->dvfs_rail->reg) &&
 			  (clk_get_rate_locked(c) < rate)) {
@@ -852,7 +852,7 @@ static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate)
 				" ready may overclock CPU\n");
 			return -ENOSYS;
 		}
-#endif /* CONFIG_MACH_COLIBRI_T30 */
+#endif /* !CONFIG_MACH_APALIS_T30 & !CONFIG_MACH_COLIBRI_T30 */
 	}
 
 	/*
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index ae6693a2a012..3f55d34e3f39 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1120,3 +1120,4 @@ p852			MACH_P852		P852			3667
 e1853 			MACH_E1853		E1853			4241
 tai			MACH_TAI		TAI			4311
 colibri_t30		MACH_COLIBRI_T30	COLIBRI_T30		4493
+apalis_t30		MACH_APALIS_T30		APALIS_T30		4513