diff options
| author | Anson Huang <b20788@freescale.com> | 2012-10-09 15:30:20 -0400 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-10-09 15:40:32 -0400 |
| commit | d9a5a4033656d5290b627aa94bf03821b64abb13 (patch) | |
| tree | 20f286860f953efec3511725c04c0a6e42ddee94 /arch/arm | |
| parent | ea2d0606fb7e7b3ed162e95736b8f78a986b4235 (diff) | |
ENGR00227477 mx6qdl: system resume fail due to DDR not accessable
For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-mx6/mx6_suspend.S | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index e8fd2b259aae..1987581e56aa 100644 --- a/arch/arm/mach-mx6/mx6_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -1262,6 +1262,9 @@ fifo_reset2_wait: bne fifo_reset2_wait ddr_io_restore_done: + ldr r1, =MMDC_P0_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + /* Ensure DDR exits self-refresh. */ ldr r6, [r1, #0x404] bic r6, r6, #0x200000 @@ -1402,6 +1405,8 @@ dsm_fifo_reset2_wait: bne dsm_fifo_reset2_wait ddr_io_restore_dsm_done: + ldr r1, =MMDC_P0_BASE_ADDR + /* Ensure DDR exits self-refresh. */ ldr r6, [r1, #0x404] bic r6, r6, #0x200000 @@ -1531,11 +1536,11 @@ restore control register to enable cache #endif mov r8, lr - push {r0-r12} + push {r0-r3, r12} /* Set up the per-CPU stacks */ bl cpu_init - pop {r0-r12} + pop {r0-r3, r12} /* * Restore the MMU table entry that was modified for |