tegra framebuffer - dsi one shot support

DSI one shot support requires register access in the tegra framebuffer to
poke the frame trigger bit (with both the trigger bit and the tearing effect
signal are high, a frame of pixels will be sent to the panel). The boot args
must also be expanded to have a "use tearing effect" flag.

tegra RM: Expanded Display clock configuration options.

Added an option for restricted Display clock synchronization with MIPI
PLL - select MIPI PLL as a pixel clock source, but preserve PLL settings.
To specify this option flag NvRmClockConfig_InternalClockForPads should
be set by RM client along with NvRmClockConfig_MipiSync flag (in the
absence of the former flag, MIPI PLL can be re-configured at RM discretion
- current behavior).

Change-Id: I495c2d76656efe8653aa5731c07180c2bfcd2fc0
Reviewed-on: http://git-master/r/2342
Tested-by: Arthur Spence <aspence@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

4 files changed, 36 insertions, 10 deletions

diff --git a/arch/arm/mach-tegra/include/nvbootargs.h b/arch/arm/mach-tegra/include/nvbootargs.h
index 908c26f0ea52..2e11843a9a68 100644
--- a/arch/arm/mach-tegra/include/nvbootargs.h
+++ b/arch/arm/mach-tegra/include/nvbootargs.h
@@ -94,6 +94,7 @@ typedef struct NvBootArgsCarveoutRec
  */
 typedef struct NvBootArgsWarmbootRec
 {
+    /* The key used for accessing the preserved memory handle */
     NvU32 MemHandleKey;
 } NvBootArgsWarmboot;
 
@@ -112,7 +113,6 @@ typedef struct NvBootArgsPreservedMemHandleRec
     NvU32   Size;
 } NvBootArgsPreservedMemHandle;
 
-
 /**
  * Display boot args, indexed by NvBootArgKey_Display.
  *
@@ -162,6 +162,16 @@ typedef struct NvBootArgsFramebufferRec
      *  assumed to begin at Pitch * Height bytes from the
      *  previous surface.  */
     NvU8  NumSurfaces;
+    /* Flags for future expandability.
+     * Current allowable flags are:
+     * zero - default
+     * NV_BOOT_ARGS_FB_FLAG_TEARING_EFFECT - use a tearing effect signal in
+     *      combination with a trigger from the display software to generate
+     *      a frame of pixels for the display device.
+     */
+    NvU32 Flags;
+#define NVBOOTARG_FB_FLAG_TEARING_EFFECT (0x1)
+
 } NvBootArgsFramebuffer;
 
 /**
@@ -210,8 +220,8 @@ typedef struct NvBootArgsChipShmooPhysRec
     NvU32 Size;
 } NvBootArgsChipShmooPhys;
 
-#define NVBOOTARG_NUM_PRESERVED_HANDLES (NvBootArgKey_PreservedMemHandle_Num - \
-                                         NvBootArgKey_PreservedMemHandle_0)
+#define NVBOOTARG_NUM_PRESERVED_HANDLES \
+    (NvBootArgKey_PreservedMemHandle_Num - NvBootArgKey_PreservedMemHandle_0)
 
 /**
  * OS-agnostic bootarg structure.
diff --git a/arch/arm/mach-tegra/include/nvrm_power.h b/arch/arm/mach-tegra/include/nvrm_power.h
index e8be8c9bf4cf..34b3b335d40f 100644
--- a/arch/arm/mach-tegra/include/nvrm_power.h
+++ b/arch/arm/mach-tegra/include/nvrm_power.h
@@ -175,7 +175,13 @@ typedef enum
     /// - Target SPDIF: configure SPDIFIN only
         NvRmClockConfig_SubConfig = 0x20,
  
-    /// Use MIPI PLL as Display clock source
+    /// Select MIPI PLL as clock source
+    /// - Target Display:
+    ///  (a) NvRmClockConfig_InternalClockForPads is also specified -
+    ///      use MIPI PLL for pixel clock source, preserve PLL configuration
+    ///  (b) NvRmClockConfig_InternalClockForPads is not specified -
+    ///      use MIPI PLL for pixel clock source, re-configure it if necessary
+    /// - Target HDMI: use MIPI PLL as HDMI clock source
         NvRmClockConfig_MipiSync = 0x40,
  
     /// Adjust Audio PLL to match requested I2S or SPDIF frequency
diff --git a/arch/arm/mach-tegra/nvos/nvos.c b/arch/arm/mach-tegra/nvos/nvos.c
index 9c45e1a255ba..27a0fcf683ca 100644
--- a/arch/arm/mach-tegra/nvos/nvos.c
+++ b/arch/arm/mach-tegra/nvos/nvos.c
@@ -1540,8 +1540,7 @@ NvError NvOsBootArgGet(NvU32 key, void *arg, NvU32 size)
     }
     else
     {
-        switch (key)
-        {
+        switch (key) {
         case NvBootArgKey_ChipShmoo:
             src = &s_BootArgs.ChipShmooArgs;
             size_src = sizeof(NvBootArgsChipShmoo);
@@ -1573,10 +1572,19 @@ NvError NvOsBootArgGet(NvU32 key, void *arg, NvU32 size)
         }
     }
 
-    if (!arg || !src || (size_src!=size))
+    if( !arg || !src )
+    {
         return NvError_BadParameter;
+    }
 
-    NvOsMemcpy(arg, src, size_src);
+    /* don't copy too much if the size has changed (gotten bigger in new
+     * binaries.
+     */
+    NvOsMemcpy(arg, src, NV_MIN( size, size_src) );
+    if( size > size_src )
+    {
+        NvOsMemset( (NvU8 *)src + size_src, 0, size - size_src );
+    }
     return NvSuccess;
 }
 
diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
index f13ef4797306..ca63729f2673 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c
@@ -1106,9 +1106,11 @@ Ap15DisplayClockConfigure(
      */
     if (flags & NvRmClockConfig_MipiSync)
     {
-        // PLLD requested
+        // PLLD requested - use it as a source, and reconfigure,
+        //  unless it is also routed to the pads
         SourceId = NvRmClockSource_PllD0;
-        Ap15PllDConfigure(hRmDevice, TargetFreq);
+        if (!(flags & NvRmClockConfig_InternalClockForPads))
+            Ap15PllDConfigure(hRmDevice, TargetFreq);
     }
     else if (NvRmIsFreqRangeReachable(
         SourceClockFreq, MinFreq, MaxFreq, NVRM_DISPLAY_DIVIDER_MAX))