diff options
| author | Ninad Malwade <nmalwade@nvidia.com> | 2010-03-02 16:37:27 +0530 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-03-02 20:28:36 -0800 |
| commit | 0d9388dc448edfd80a7d073cc7dc8c23384f7f42 (patch) | |
| tree | 0fb471cab41f604c1b3253c2ee68981650593e9e /arch/arm | |
| parent | 50531c4fa704750ff71a51ebc1ce95a7c465cf54 (diff) | |
tegra:EC receive a transaction request that slave address 0 from T20
- Sometimes AP acts as a I2C master and drives address
lines to 0 causing transaction errors.
- Enable NEW_MASTER_FSM in slave as suggested
- Already verified on harmony + ce6
- Bug 614917
Change-Id: I0563e8472fc4bd5b1fb0d8c9e9508b6a39b68d76
Reviewed-on: http://git-master/r/727
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/nvec/smbus/nvec_i2c_transport.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvec/smbus/nvec_i2c_transport.c b/arch/arm/mach-tegra/nvec/smbus/nvec_i2c_transport.c index 4f47bc1fc566..ebe6d744f422 100644 --- a/arch/arm/mach-tegra/nvec/smbus/nvec_i2c_transport.c +++ b/arch/arm/mach-tegra/nvec/smbus/nvec_i2c_transport.c @@ -670,6 +670,13 @@ static NvError HwI2cInitController(NvRmI2cSlaveController* t) I2C_REGW(t, I2C_SL_ADDR2, 0); // Set Delay count register I2C_REGW(t, I2C_SL_DELAY_COUNT, DELAY_COUNT); + // Enable NEW_MASTER_FSM in slave for T20 + // It is found that in some corner case, it appears that the slave is + // driving '0' on the bus and the HW team suggested to enable new master + // even if it is not used as old master is known to go into + // bad state + SlaveConfig = NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE); + I2C_REGW(t, I2C_CNFG, SlaveConfig); // Enable Ack and disable response to general call. SlaveConfig = ENABLE_I2C_SLAVE(t); //NvOsDebugPrintf("\n***SlaveConfig=0x%x", SlaveConfig); @@ -954,6 +961,13 @@ NvError NvEcTransportPowerResume(NvEcTransportHandle t) // Set the slave address and 7-bit address mode. I2C_REGW(t, I2C_SL_ADDR1, (t->SlaveAddress >> 1)); I2C_REGW(t, I2C_SL_ADDR2, 0); + // Enable NEW_MASTER_FSM in slave for T20 + // It is found that in some corner case, it appears that the slave is + // driving '0' on the bus and the HW team suggested to enable new master + // even if it is not used as old master is known to go into + // bad state + SlaveConfig = NV_DRF_DEF(I2C, I2C_CNFG, NEW_MASTER_FSM, ENABLE); + I2C_REGW(t, I2C_CNFG, SlaveConfig); // Enable Ack and disable response to general call. SlaveConfig = ENABLE_I2C_SLAVE(t); I2C_REGW(t, I2C_SL_CNFG, SlaveConfig); |