diff options
| author | Johnny Qiu <joqiu@nvidia.com> | 2012-02-03 14:32:54 +0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-02-16 06:53:06 -0800 |
| commit | 35e18e9d2be87007ab0efcf6130ad2c3546e73f7 (patch) | |
| tree | 0f5b23b8d6287bb67b5f0849574026e2ad1de8ea /arch/arm | |
| parent | fe1c6f10c77a95d703b4ea01964fda3a9316fd05 (diff) | |
arm: tegra: kai: Specify PLLD2 as backup clock source
Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz)
can provide accurate enough pixel clock rate for kai panel, use
PLLD2 as backup clock source.
Bug 928260
Change-Id: I2f268a1551611a9170e86cbdc44a5302edabc9f0
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/83738
Reviewed-by: Liangchuan Mi <lmi@nvidia.com>
Tested-by: Liangchuan Mi <lmi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/board-kai-panel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-kai-panel.c b/arch/arm/mach-tegra/board-kai-panel.c index 0b1cba2e44b2..e1a5ad5140f0 100644 --- a/arch/arm/mach-tegra/board-kai-panel.c +++ b/arch/arm/mach-tegra/board-kai-panel.c @@ -520,6 +520,7 @@ static struct tegra_dc_out kai_disp1_out = { .order = TEGRA_DC_ORDER_RED_BLUE, .sd_settings = &kai_sd_settings, .parent_clk = "pll_p", + .parent_clk_backup = "pll_d2_out0", .type = TEGRA_DC_OUT_RGB, .depth = 18, |