i.MX6: mx6q_sabrelite: add SD2+WiFi pad setup

2 files changed, 98 insertions, 1 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index 38510b631012..36d15e7e8034 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -100,6 +100,10 @@
 #define N6_WL1271_WL_EN			IMX_GPIO_NR(6, 15)
 #define N6_WL1271_BT_EN			IMX_GPIO_NR(6, 16)
 
+#define MX6Q_SABRELITE_WL_IRQ_TEST_PADCFG	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6Q_SABRELITE_WL_IRQ_PADCFG	(PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6Q_SABRELITE_WL_EN_PADCFG	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
 #define MX6Q_SABRELITE_SD3_WP_PADCFG	(PAD_CTL_PKE | PAD_CTL_PUE |	\
 		PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED |	\
 		PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
@@ -320,6 +324,11 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
 	MX6Q_PAD_EIM_D26__UART2_TXD,
 	MX6Q_PAD_EIM_D27__UART2_RXD,
 
+	/* WL127X pads */
+	NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS1__GPIO_6_14, MX6Q_SABRELITE_WL_IRQ_PADCFG),	/* wl1271 wl_irq */
+	NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS2__GPIO_6_15, MX6Q_SABRELITE_WL_EN_PADCFG),	/* wl1271 wl_en */
+	NEW_PAD_CTRL(MX6Q_PAD_NANDF_CS3__GPIO_6_16, MX6Q_SABRELITE_WL_EN_PADCFG),	/* wl1271 bt_en */
+
 	/* UART3 for wl1271 */
 	MX6Q_PAD_EIM_D24__UART3_TXD,
 	MX6Q_PAD_EIM_D25__UART3_RXD,
@@ -333,6 +342,14 @@ static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
 	MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC,
 	MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC,
 
+	/* USDHC2 */
+	MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ,
+	MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ,
+	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ,
+	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ,
+	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ,
+	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ,
+
 	/* USDHC3 */
 	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
 	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
@@ -399,6 +416,9 @@ mx6q_sd##id##_##speed##mhz[] = {		\
 	MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,	\
 }
 
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 50);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 100);
+static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(2, 200);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
@@ -426,6 +446,15 @@ static int plt_sd_pad_change(unsigned int index, int clock)
 	u32 sd_pads_50mhz_cnt;
 
 	switch (index) {
+	case 1:
+		sd_pads_200mhz = mx6q_sd2_200mhz;
+		sd_pads_100mhz = mx6q_sd2_100mhz;
+		sd_pads_50mhz = mx6q_sd2_50mhz;
+
+		sd_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd2_200mhz);
+		sd_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd2_100mhz);
+		sd_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd2_50mhz);
+		break;
 	case 2:
 		sd_pads_200mhz = mx6q_sd3_200mhz;
 		sd_pads_100mhz = mx6q_sd3_100mhz;
@@ -473,6 +502,15 @@ static int plt_sd_pad_change(unsigned int index, int clock)
 	}
 }
 
+static struct esdhc_platform_data mx6q_sabrelite_sd2_data = {
+	.always_present = 1,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.keep_power_at_suspend = 0,
+	.caps = MMC_CAP_POWER_OFF_CARD,
+	.platform_pad_change = plt_sd_pad_change,
+};
+
 static struct esdhc_platform_data mx6q_sabrelite_sd3_data = {
 	.cd_gpio = MX6Q_SABRELITE_SD3_CD,
 	.wp_gpio = MX6Q_SABRELITE_SD3_WP,
@@ -1251,7 +1289,6 @@ static void __init mx6_sabrelite_board_init(void)
 	if (isn6)
 		imx6q_add_imx_uart(2, &mx6_arm2_uart2_data);
 
-	mx6q_sabrelite_init_uart();
 	imx6q_add_mxc_hdmi_core(&hdmi_core_data);
 
 	imx6q_add_ipuv3(0, &ipu_data[0]);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index 9226af18f7ee..83f288137a73 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -2909,6 +2909,24 @@
 #define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE		\
 		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
 
+#define _MX6Q_PAD_SD2_CMD__USDHC3_CMD			\
+		IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CLK__USDHC3_CLK			\
+		IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT0__USDHC3_DAT0			\
+		IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT1__USDHC3_DAT1			\
+		IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT2__USDHC3_DAT2			\
+		IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT3__USDHC3_DAT3			\
+		IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+
 #define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7			\
 		IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
 #define _MX6Q_PAD_SD3_DAT7__UART1_TXD			\
@@ -6517,6 +6535,48 @@
 #define  MX6Q_PAD_TEST_MODE__TCU_TEST_MODE		\
 		(_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
 
+#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD_50MHZ		\
+		(_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD_100MHZ		\
+		(_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD_200MHZ		\
+		(_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
+#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK_50MHZ		\
+		(_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK_100MHZ		\
+		(_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK_200MHZ		\
+		(_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
+#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_50MHZ		\
+		(_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_100MHZ	\
+		(_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0_200MHZ	\
+		(_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
+#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_50MHZ		\
+		(_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_100MHZ		\
+		(_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1_200MHZ		\
+		(_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
+#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_50MHZ		\
+		(_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_100MHZ		\
+		(_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2_200MHZ		\
+		(_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
+#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_50MHZ		\
+		(_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_100MHZ		\
+		(_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
+#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3_200MHZ		\
+		(_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
+
 #define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ		\
 		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
 #define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ		\