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authorStefan Agner <stefan@agner.ch>2015-08-31 15:20:01 -0700
committerStefan Agner <stefan@agner.ch>2015-08-31 15:20:01 -0700
commitf0a5b778a1676bed3d9760823bfeb2b18aee74f4 (patch)
treea29b499bd80f35418b65605c4c811c8591b0128b /arch/arm
parent58c887f04ea87c470e25dcd26642479066c762d6 (diff)
ARM: dts: vf610: resync NFC bindings with latest upstream patch
Resync with latest upstream patchset v11. This introduces enhanced device tree bindings where NAND chips need to be specified as sub- nodes of the controller.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi21
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi2
2 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index a638dfd5aca4..5c4b91fa8229 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -93,14 +93,21 @@
&nfc {
assigned-clocks = <&clks VF610_CLK_NFC>;
assigned-clock-rates = <33000000>;
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-ecc-step-size = <2048>;
- nand-ecc-strength = <32>;
- nand-on-flash-bbt;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nfc_1>;
+ pinctrl-0 = <&pinctrl_nfc>;
status = "okay";
+
+ nand@0 {
+ compatible = "fsl,vf610-nfc-nandcs";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <32>;
+ nand-ecc-step-size = <2048>;
+ nand-on-flash-bbt;
+ };
};
&pwm0 {
@@ -299,7 +306,7 @@
>;
};
- pinctrl_nfc_1: nfcgrp_1 {
+ pinctrl_nfc: nfcgrp {
fsl,pins = <
VF610_PAD_PTD23__NF_IO7 0x28df
VF610_PAD_PTD22__NF_IO6 0x28df
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 3551059ccc80..eb4217273c0e 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -672,6 +672,8 @@
};
nfc: nand@400e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,vf610-nfc";
reg = <0x400e0000 0x4000>;
interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;