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authorDaehyoung Ko <dko@nvidia.com>2011-09-30 17:42:49 -0700
committerSimone Willett <swillett@nvidia.com>2011-10-11 17:04:04 -0700
commite7f7abc919b18b3630aec33115be717f3c5597a8 (patch)
tree01a85a76373053dff21b4db112b7c995e48b7f82 /arch/arm
parentef252c33adcd9d24037c8ba5f47b3af9395e7288 (diff)
ARM tegra: gpio: Correct gpio interrupt init sequence
It is possible for GPIO interrupt to occur when registering handler since set_irq_chained_handler enables GPIO interrupt. Thus all relevant variables are required to be initialized before calling set_irq_chained_handler. Also add initialization of interrupt status register. Bug 884569 Reviewed-on: http://git-master/r/55612 (cherry picked from commit e03fe4cc1bf06fa6c32c0520e2ba31f009f9301d) Change-Id: I32ea97c254fe537d5a86e630a0de9afcf117f96e Reviewed-on: http://git-master/r/56750 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/gpio.c8
-rw-r--r--arch/arm/mach-tegra/legacy_irq.c1
2 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 9066f8102103..3ba21ca8e7e0 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -416,6 +416,7 @@ static int __init tegra_gpio_init(void)
for (j = 0; j < 4; j++) {
int gpio = tegra_gpio_compose(i, j, 0);
__raw_writel(0x00, GPIO_INT_ENB(gpio));
+ __raw_writel(0x00, GPIO_INT_STA(gpio));
}
}
@@ -434,11 +435,12 @@ static int __init tegra_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
bank = &tegra_gpio_banks[i];
- set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
- set_irq_data(bank->irq, bank);
-
for (j = 0; j < 4; j++)
spin_lock_init(&bank->lvl_lock[j]);
+
+ set_irq_data(bank->irq, bank);
+ set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
+
}
return 0;
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
index eba0073e4f02..41ed85401073 100644
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ b/arch/arm/mach-tegra/legacy_irq.c
@@ -178,6 +178,7 @@ void tegra_init_legacy_irq(void)
void __iomem *ictlr = ictlr_reg_base[i];
writel(~0, ictlr + ICTLR_CPU_IER_CLR);
writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+ writel(~0, ictlr + ICTLR_CPU_IEP_FIR_CLR);
}
}