diff options
| author | Frank Li <Frank.Li@freescale.com> | 2010-02-02 12:46:26 +0800 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-05-25 11:17:14 +0200 |
| commit | db70d82e0ffca29ecb2a24602ff200bd6df2ca53 (patch) | |
| tree | 7531cecf7f3f5d72fbcebda4d717620491f608ad /arch/arm | |
| parent | e6ea0df1c331628c735044079008e743125f557e (diff) | |
ENGR00120882 MX23 new MSL base on plat-mxs
Add mx23 evk msl base on plat-mxs
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm')
43 files changed, 10586 insertions, 1 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 624af95ebcf3..3ca5dd71b3ae 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -137,6 +137,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX28) := mx28 +machine-$(CONFIG_ARCH_MX23) := mx23 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX35) := mx35 machine-$(CONFIG_ARCH_MX37) := mx37 diff --git a/arch/arm/configs/mx23evk_defconfig b/arch/arm/configs/mx23evk_defconfig new file mode 100644 index 000000000000..76f2a2a15363 --- /dev/null +++ b/arch/arm/configs/mx23evk_defconfig @@ -0,0 +1,998 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31 +# Tue Feb 9 11:24:57 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_DMA_ZONE_SIZE=12 + +# +# Freescale i.MXS implementations +# +# CONFIG_ARCH_MX28 is not set +CONFIG_ARCH_MX23=y +CONFIG_MACH_MX23EVK=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +# CONFIG_MXS_AUART0_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +# CONFIG_MXS_AUART1_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +# CONFIG_MXS_AUART2_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +# CONFIG_MXS_AUART3_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +# CONFIG_MXS_AUART4_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART4_DMA_ENABLE is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/mmcblk0p2 rootwait lcd_panel=lms350" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_UNIX is not set +# CONFIG_NET_KEY is not set +# CONFIG_INET is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_MXS is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MXS is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +# CONFIG_SERIAL_MXS_AUART is not set +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/mach-mx23/Kconfig b/arch/arm/mach-mx23/Kconfig new file mode 100644 index 000000000000..0a122b009687 --- /dev/null +++ b/arch/arm/mach-mx23/Kconfig @@ -0,0 +1,9 @@ +choice + prompt "Select i.MXS board type" + +config MACH_MX23EVK + bool "Freescale MX23 EVK board" + depends on ARCH_MX23 + select USB_ARCH_HAS_EHCI + +endchoice diff --git a/arch/arm/mach-mx23/Makefile b/arch/arm/mach-mx23/Makefile new file mode 100644 index 000000000000..a7a7c53d387d --- /dev/null +++ b/arch/arm/mach-mx23/Makefile @@ -0,0 +1,14 @@ +# +# Makefile for the linux kernel. +# +obj-y += pinctrl.o clock.o device.o serial.o + +# Board select +obj-$(CONFIG_MACH_MX23EVK) += mx23evk.o mx23evk_pins.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o + +# USB support +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o diff --git a/arch/arm/mach-mx23/Makefile.boot b/arch/arm/mach-mx23/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-mx23/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c new file mode 100644 index 000000000000..c2ea53e71e3a --- /dev/null +++ b/arch/arm/mach-mx23/clock.c @@ -0,0 +1,603 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/clock.h> + +#include "regs-clkctrl.h" +#include "regs-digctl.h" + +#include "mach/mx23.h" + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) + +/* external clock input */ +static struct clk xtal_clk[]; +static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; + +static unsigned long enet_mii_phy_rate; + +static int mx23_raw_enable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } + return 0; +} + +static void mx23_raw_disable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } +} + +static unsigned long xtal_get_rate(struct clk *clk) +{ + int id = clk - xtal_clk; + return xtal_clk_rate[id]; +} + +static struct clk xtal_clk[] = { + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, +}; + +static struct clk ref_xtal_clk = { + .parent = &xtal_clk[0], +}; + +static unsigned long pll_get_rate(struct clk *clk); +static int pll_enable(struct clk *clk); +static void pll_disable(struct clk *clk); + +static struct clk pll_clk = { + + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .enable = pll_enable, + .disable = pll_disable, + +}; + +static unsigned long pll_get_rate(struct clk *clk) +{ + return 480000000; +} + +static int pll_enable(struct clk *clk) +{ + int timeout = 100; + unsigned long reg; + + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLLCTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLLCTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; +} + +static void pll_disable(struct clk *clk) +{ + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR); + return; +} + +static inline unsigned long +ref_clk_get_rate(unsigned long base, unsigned int div) +{ + unsigned long rate = base / 1000; + return 1000 * ((rate * 18) / div); +} + +static unsigned long ref_cpu_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_CPUFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_cpu_clk = { + .parent = &pll_clk, + .get_rate = ref_cpu_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATECPU, +}; + +static unsigned long ref_emi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_EMIFRAC; + reg >>= BP_CLKCTRL_FRAC_EMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_emi_clk = { + .parent = &pll_clk, + .get_rate = ref_emi_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEEMI, +}; + +static unsigned long ref_io_get_rate(struct clk *clk); +static struct clk ref_io_clk = { + .parent = &pll_clk, + .get_rate = ref_io_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO, +}; + +static unsigned long ref_io_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_IOFRAC; + reg >>= BP_CLKCTRL_FRAC_IOFRAC; + + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static unsigned long ref_pix_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_PIXFRAC; + reg >>= BP_CLKCTRL_FRAC_PIXFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + + +static struct clk ref_pix_clk = { + .parent = &pll_clk, + .get_rate = ref_pix_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEPIX, +}; + +static unsigned long cpu_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + if (clk->parent == &ref_cpu_clk) + reg = (reg & BM_CLKCTRL_CPU_DIV_CPU) >> BP_CLKCTRL_CPU_DIV_CPU; + else + reg = (reg & BM_CLKCTRL_CPU_DIV_XTAL) >> + BP_CLKCTRL_CPU_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk cpu_clk = { + .parent = &ref_cpu_clk, + .get_rate = cpu_get_rate, +}; + +static unsigned long uart_get_rate(struct clk *clk) +{ + unsigned int div; + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) & + BM_CLKCTRL_XTAL_DIV_UART; + return clk->parent->get_rate(clk->parent) / div; +} + +static struct clk uart_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE, + .get_rate = uart_get_rate, +}; + +static struct clk pwm_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE, +}; + + +static unsigned long clk_32k_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static struct clk clk_32k = { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE, + .get_rate = clk_32k_get_rate, +}; + +static unsigned long lradc_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 16; +} + +static struct clk lradc_clk = { + .parent = &clk_32k, + .flags = RATE_FIXED, + .get_rate = lradc_get_rate, +}; + +static unsigned long x_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS) & + BM_CLKCTRL_XBUS_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk x_clk = { + .parent = &ref_xtal_clk, + .get_rate = x_get_rate, +}; + +static struct clk ana_clk = { + .parent = &ref_xtal_clk, +}; + +static unsigned long rtc_get_rate(struct clk *clk) +{ + if (clk->parent == &xtal_clk[2]) + return clk->parent->get_rate(clk->parent); + return clk->parent->get_rate(clk->parent) / 768; +} + +static struct clk rtc_clk = { + .parent = &ref_xtal_clk, + .get_rate = rtc_get_rate, +}; + +static unsigned long h_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk h_clk = { + .parent = &cpu_clk, + .get_rate = h_get_rate, +}; + +static struct clk ocrom_clk = { + .parent = &h_clk, +}; + +static unsigned long emi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI); + if (clk->parent == &ref_emi_clk) + reg = (reg & BM_CLKCTRL_EMI_DIV_EMI); + else + reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static struct clk emi_clk = { + .parent = &ref_emi_clk, + .get_rate = emi_get_rate, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .enable_bits = BM_CLKCTRL_EMI_CLKGATE, +}; + +static unsigned long ssp_get_rate(struct clk *clk); + +static int ssp_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + int div = (clk_get_rate(clk->parent) + rate - 1) / rate; + u32 reg_frac; + const int mask = 0x1FF; + int try = 10; + int i = -1; + + if (div == 0 || div > mask) + goto out; + + reg_frac = __raw_readl(clk->scale_reg); + reg_frac &= ~(mask << clk->scale_bits); + + while (try--) { + __raw_writel(reg_frac | (div << clk->scale_bits), + clk->scale_reg); + + if (clk->busy_reg) { + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + } + if (i) + break; + } + + if (!i) + ret = -ETIMEDOUT; + else + ret = 0; + +out: + if (ret != 0) + printk(KERN_ERR "%s: error %d\n", __func__, ret); + return ret; +} + +static int ssp_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + else + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + + ret = 0; + } + + return ret; +} + +static struct clk ssp_clk[] = { + { + .parent = &ref_io_clk, + .get_rate = ssp_get_rate, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .enable_bits = BM_CLKCTRL_SSP_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 3, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, +}; + +static unsigned long ssp_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP) & + BM_CLKCTRL_SSP_DIV; + + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->get_rate(clk->parent); + long div; + + div = (__raw_readl(clk->scale_reg) >> clk->scale_bits) & + BM_CLKCTRL_PIX_DIV; + if (div) + rate /= div; + + return rate; +} + +static int lcdif_set_rate(struct clk *clk, unsigned long rate) +{ + int reg_val; + + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); + reg_val |= (1 << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV; + __raw_writel(reg_val, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + } + + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + reg_val |= BM_CLKCTRL_CLKSEQ_BYPASS_PIX; + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + + return 0; +} + +static struct clk dis_lcdif_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .busy_bits = 29, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .enable_bits = 31, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 14, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, +}; + +/* usb_clk for usb0 */ +static struct clk usb_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB_CLKGATE, +}; + + +static struct clk_lookup onchip_clocks[] = { + { + .con_id = "xtal.0", + .clk = &xtal_clk[0], + }, + { + .con_id = "xtal.1", + .clk = &xtal_clk[1], + }, + { + .con_id = "xtal.2", + .clk = &xtal_clk[2], + }, + { + .con_id = "pll.0", + .clk = &pll_clk, + }, + { + .con_id = "ref_xtal", + .clk = &ref_xtal_clk, + }, + { + .con_id = "ref_cpu", + .clk = &ref_cpu_clk, + }, + { + .con_id = "ref_emi", + .clk = &ref_emi_clk, + }, + { + .con_id = "ref_io.0", + .clk = &ref_io_clk, + }, + { + .con_id = "ref_pix", + .clk = &ref_pix_clk, + }, + { + .con_id = "rtc", + .clk = &rtc_clk, + }, + { + .con_id = "cpu", + .clk = &cpu_clk, + }, + { + .con_id = "h", + .clk = &h_clk, + }, + { + .con_id = "x", + .clk = &x_clk, + }, + { + .con_id = "ocrom", + .clk = &ocrom_clk, + }, + { + .con_id = "clk_32k", + .clk = &clk_32k, + }, + { + .con_id = "uart", + .clk = &uart_clk, + }, + { + .con_id = "pwm", + .clk = &pwm_clk, + }, + { + .con_id = "lradc", + .clk = &lradc_clk, + }, + { + .con_id = "emi", + .clk = &emi_clk, + }, + { + .con_id = "usb_clk0", + .clk = &usb_clk, + } +}; + + +static void mx23_clock_scan(void) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) + cpu_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) + dis_lcdif_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + emi_clk.parent = &ref_xtal_clk; +}; + + +void __init mx23_set_input_clk(unsigned long xtal0, + unsigned long xtal1, + unsigned long xtal2, unsigned long enet) +{ + xtal_clk_rate[0] = xtal0; + xtal_clk_rate[1] = xtal1; + xtal_clk_rate[2] = xtal2; +} + +void __init mx23_clock_init(void) +{ + int i; + mx23_clock_scan(); + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) + clk_register(&onchip_clocks[i]); + + clk_enable(&cpu_clk); + clk_enable(&emi_clk); +} diff --git a/arch/arm/mach-mx23/device.c b/arch/arm/mach-mx23/device.c new file mode 100644 index 000000000000..5a4675a1f9f6 --- /dev/null +++ b/arch/arm/mach-mx23/device.c @@ -0,0 +1,421 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/mmc/host.h> +#include <linux/phy.h> +#include <linux/fec.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/regs-timrot.h> +#include <mach/regs-lradc.h> +#include <mach/device.h> +#include <mach/dma.h> +#include <mach/lradc.h> +#include <mach/lcdif.h> + +#include "device.h" +#include "mx23_pins.h" +#include "mach/mx23.h" + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct resource duart_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DUART_PHYS_ADDR, + .end = DUART_PHYS_ADDR + 0x1000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_DEBUG_UART , + .end = IRQ_DEBUG_UART , + }, +}; + +static void __init mx23_init_duart(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-duart", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = duart_resource; + pdev->num_resources = ARRAY_SIZE(duart_resource); + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_duart(void) +{ +} +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct resource mxs_ahb_apbh_res = { + .flags = IORESOURCE_MEM, + .start = APBH_DMA_PHYS_ADDR, + .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = 16, +}; + +static struct resource mxs_ahb_apbx_res = { + .flags = IORESOURCE_MEM, + .start = APBX_DMA_PHYS_ADDR, + .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbx_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBX, + .chan_num = 16, +}; + +static void __init mx23_init_dma(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + lookup = mxs_get_devices("mxs-dma"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + if (!strcmp(pdev->name, "mxs-dma-apbh")) { + pdev->resource = &mxs_ahb_apbh_res; + pdev->dev.platform_data = &mxs_ahb_apbh_data; + } else if (!strcmp(pdev->name, "mxs-dma-apbx")) { + pdev->resource = &mxs_ahb_apbx_res; + pdev->dev.platform_data = &mxs_ahb_apbx_data; + } else + continue; + pdev->num_resources = 1; + mxs_add_device(pdev, 0); + } +} +#else +static void mx23_init_dma(void) +{ + ; +} +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) +static struct resource framebuffer_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = LCDIF_PHYS_ADDR, + .end = LCDIF_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF, + .end = IRQ_LCDIF, + }, +}; + +static struct mxs_platform_fb_data mxs_framebuffer_pdata = { + .list = LIST_HEAD_INIT(mxs_framebuffer_pdata.list), +}; + +static void __init mx23_init_lcdif(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = framebuffer_resource; + pdev->num_resources = ARRAY_SIZE(framebuffer_resource); + pdev->dev.platform_data = &mxs_framebuffer_pdata; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_lcdif(void) +{ + ; +} +#endif + + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) +static struct resource mx23_wdt_res = { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, +}; + +static void __init mx23_init_wdt(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-wdt", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = &mx23_wdt_res; + pdev->num_resources = 1; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_wdt(void) +{ + ; +} +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) +static struct resource mx23_rtc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_1MSEC, + .end = IRQ_RTC_1MSEC, + }, +}; + +static void __init mx23_init_rtc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-rtc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_rtc_res; + pdev->num_resources = ARRAY_SIZE(mx23_rtc_res); + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_rtc(void) +{ + ; +} +#endif + +#ifdef CONFIG_MXS_LRADC +struct mxs_lradc_plat_data mx23_lradc_data = { + .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10, + .battery_voltage = BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7, +}; + +static struct resource mx23_lradc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void __init mx23_init_lradc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-lradc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_lradc_res; + pdev->num_resources = ARRAY_SIZE(mx23_lradc_res); + pdev->dev.platform_data = &mx23_lradc_data; + mxs_add_device(pdev, 0); +} +#else +static void __init mx23_init_lradc(void) +{ + ; +} +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) +static struct mxskbd_keypair keyboard_data[] = { + { 100, KEY_F4 }, + { 306, KEY_F5 }, + { 626, KEY_F6 }, + { 932, KEY_F7 }, + { 1260, KEY_F8 }, + { 1584, KEY_F9 }, + { 1907, KEY_F10 }, + { 2207, KEY_F11 }, + { 2525, KEY_F12 }, + { 2831, KEY_F13}, + { 3134, KEY_F14 }, + { -1, 0 }, +}; + +static struct mxs_kbd_plat_data mxs_kbd_data = { + .keypair = keyboard_data, + .channel = LRADC_CH1, +}; + +static struct resource mx23_kbd_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH1, + .end = IRQ_LRADC_CH1, + }, +}; + +static void __init mx23_init_kbd(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-kbd", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_kbd_res; + pdev->num_resources = ARRAY_SIZE(mx23_kbd_res); + pdev->dev.platform_data = &mxs_kbd_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_kbd(void) +{ + ; +} +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) +static struct mxs_touchscreen_plat_data mx23_ts_data = { + .x_plus_chan = LRADC_TOUCH_X_PLUS, + .x_minus_chan = LRADC_TOUCH_X_MINUS, + .y_plus_chan = LRADC_TOUCH_Y_PLUS, + .y_minus_chan = LRADC_TOUCH_Y_MINUS, + .x_plus_val = BM_LRADC_CTRL0_XPULSW, + .x_minus_val = BF_LRADC_CTRL0_XNURSW(2), + .y_plus_val = BF_LRADC_CTRL0_YPLLSW(1), + .y_minus_val = BM_LRADC_CTRL0_YNLRSW, + .x_plus_mask = BM_LRADC_CTRL0_XPULSW, + .x_minus_mask = BM_LRADC_CTRL0_XNURSW, + .y_plus_mask = BM_LRADC_CTRL0_YPLLSW, + .y_minus_mask = BM_LRADC_CTRL0_YNLRSW, +}; + +static struct resource mx23_ts_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_TOUCH, + .end = IRQ_LRADC_TOUCH, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH5, + .end = IRQ_LRADC_CH5, + }, +}; + +static void __init mx23_init_ts(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-ts", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_ts_res; + pdev->num_resources = ARRAY_SIZE(mx23_ts_res); + pdev->dev.platform_data = &mx23_ts_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_ts(void) +{ + ; +} +#endif +int __init mx23_device_init(void) +{ + mx23_init_duart(); + return 0; +} + +static struct __initdata map_desc mx23_io_desc[] = { + { + .virtual = MX23_SOC_IO_VIRT_BASE, + .pfn = __phys_to_pfn(MX23_SOC_IO_PHYS_BASE), + .length = MX23_SOC_IO_AREA_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init mx23_map_io(void) +{ + iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); +} + +void __init mx23_irq_init(void) +{ + avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS); +} + +static void mx23_timer_init(void) +{ + int i, reg; + mx23_clock_init(); + + mx23_timer.clk = clk_get(NULL, "clk_32k"); + if (mx23_timer.clk == NULL || IS_ERR(mx23_timer.clk)) + return; + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST, + mx23_timer.base + HW_TIMROT_ROTCTRL_CLR); + for (i = 0; i < 10000; i++) { + reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL); + if (!(reg & BM_TIMROT_ROTCTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return; + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + mx23_timer.base + HW_TIMROT_ROTCTRL_CLR); + + reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL); + + mxs_nomatch_timer_init(&mx23_timer); +} + +struct mxs_sys_timer mx23_timer = { + .timer = { + .init = mx23_timer_init, + }, + .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL, + .base = IO_ADDRESS(TIMROT_PHYS_ADDR), +}; diff --git a/arch/arm/mach-mx23/device.h b/arch/arm/mach-mx23/device.h new file mode 100644 index 000000000000..ec411552bd10 --- /dev/null +++ b/arch/arm/mach-mx23/device.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DEVICE_H__ +#define __ASM_ARCH_MACH_DEVICE_H__ + +extern struct mxs_sys_timer mx23_timer; + +extern void __init mx23_map_io(void); +extern void __init mx23_clock_init(void); +extern void __init mx23_irq_init(void); +extern int __init mx23_pinctrl_init(void); +extern int __init mx23_gpio_init(void); +extern int __init mx23_device_init(void); +extern void __init mx23_init_auart(void); +extern void __init +mx23_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long); + +#endif diff --git a/arch/arm/mach-mx23/gpio.c b/arch/arm/mach-mx23/gpio.c new file mode 100644 index 000000000000..9774664cc900 --- /dev/null +++ b/arch/arm/mach-mx23/gpio.c @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx23_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (input) + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET); + + return 0; +} + +static int mx23_gpio_get(struct mxs_gpio_port *port, int pin) +{ + unsigned int data; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + data = __raw_readl(base + HW_PINCTRL_DIN0); + return data & (1 << pin); +} + +static void mx23_gpio_set(struct mxs_gpio_port *port, int pin, int data) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (data) + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR); +} + +static unsigned int mx23_gpio_irq_stat(struct mxs_gpio_port *port) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + return mask; +} + +static int +mx23_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type) +{ + unsigned int level, pol; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level = 0; + pol = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + level = 0; + pol = 0; + break; + case IRQ_TYPE_LEVEL_HIGH: + level = 1; + pol = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + level = 1; + pol = 0; + break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + + if (level) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR); + + if (pol) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR); + + return 0; +} + +static void mx23_gpio_unmask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET); +} + +static void mx23_gpio_mask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR); +} + +static void mx23_gpio_ack_irq(struct mxs_gpio_port *port, int pin) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = 1 << pin; + mask &= __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + if (mask) + __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR); +} + +static struct mxs_gpio_port mx23_gpios[] = { + { + .irq = IRQ_GPIO0, + }, + { + .irq = IRQ_GPIO1, + }, + { + .irq = IRQ_GPIO2, + }, +}; + +static struct mxs_gpio_chip mx23_gpio_chip = { + .set_dir = mx23_gpio_direction, + .get = mx23_gpio_get, + .set = mx23_gpio_set, + .get_irq_stat = mx23_gpio_irq_stat, + .set_irq_type = mx23_gpio_set_irq_type, + .unmask_irq = mx23_gpio_unmask_irq, + .mask_irq = mx23_gpio_mask_irq, + .ack_irq = mx23_gpio_ack_irq, +}; + +int __init mx23_gpio_init(void) +{ + int i; + unsigned int reg; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL); + for (i = 0; i < ARRAY_SIZE(mx23_gpios); i++) { + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i; + if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i))) + continue; + mxs_set_gpio_chip(&mx23_gpios[i], &mx23_gpio_chip); + mx23_gpios[i].id = i; + __raw_writel(0, base + HW_PINCTRL_IRQEN0); + __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0); + mx23_gpios[i].child_irq = MXS_GPIO_IRQ_START + + (i * PINS_PER_BANK); + mxs_add_gpio_port(&mx23_gpios[i]); + } + return 0; +} diff --git a/arch/arm/mach-mx23/include/mach/dma.h b/arch/arm/mach-mx23/include/mach/dma.h new file mode 100644 index 000000000000..ad8076c5d8f3 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_UART4_RX = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_03, + MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_I2C0, + MXS_DMA_CHANNEL_AHB_APBX_I2C1, + MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx23/include/mach/irqs.h b/arch/arm/mach-mx23/include/mach/irqs.h new file mode 100644 index 000000000000..dc4e578b0e34 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/irqs.h @@ -0,0 +1,96 @@ +/* + * Freescale STMP378X interrupts + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define IRQ_DEBUG_UART 0 +#define IRQ_COMMS_RX 1 +#define IRQ_COMMS_TX 1 +#define IRQ_SSP2_ERROR 2 +#define IRQ_VDD5V 3 +#define IRQ_HEADPHONE_SHORT 4 +#define IRQ_DAC_DMA 5 +#define IRQ_DAC_ERROR 6 +#define IRQ_ADC_DMA 7 +#define IRQ_ADC_ERROR 8 +#define IRQ_SPDIF_DMA 9 +#define IRQ_SAIF2_DMA 9 +#define IRQ_SPDIF_ERROR 10 +#define IRQ_SAIF1_IRQ 10 +#define IRQ_SAIF2_IRQ 10 +#define IRQ_USB_CTRL 11 +#define IRQ_USB_WAKEUP 12 +#define IRQ_GPMI_DMA 13 +#define IRQ_SSP1_DMA 14 +#define IRQ_SSP_ERROR 15 +#define IRQ_GPIO0 16 +#define IRQ_GPIO1 17 +#define IRQ_GPIO2 18 +#define IRQ_SAIF1_DMA 19 +#define IRQ_SSP2_DMA 20 +#define IRQ_ECC8_IRQ 21 +#define IRQ_RTC_ALARM 22 +#define IRQ_UARTAPP_TX_DMA 23 +#define IRQ_UARTAPP_INTERNAL 24 +#define IRQ_UARTAPP_RX_DMA 25 +#define IRQ_I2C_DMA 26 +#define IRQ_I2C_ERROR 27 +#define IRQ_TIMER0 28 +#define IRQ_TIMER1 29 +#define IRQ_TIMER2 30 +#define IRQ_TIMER3 31 +#define IRQ_BATT_BRNOUT 32 +#define IRQ_VDDD_BRNOUT 33 +#define IRQ_VDDIO_BRNOUT 34 +#define IRQ_VDD18_BRNOUT 35 +#define IRQ_TOUCH_DETECT 36 +#define IRQ_LRADC_CH0 37 +#define IRQ_LRADC_CH1 38 +#define IRQ_LRADC_CH2 39 +#define IRQ_LRADC_CH3 40 +#define IRQ_LRADC_CH4 41 +#define IRQ_LRADC_CH5 42 +#define IRQ_LRADC_CH6 43 +#define IRQ_LRADC_CH7 44 +#define IRQ_LCDIF_DMA 45 +#define IRQ_LCDIF_ERROR 46 +#define IRQ_DIGCTL_DEBUG_TRAP 47 +#define IRQ_RTC_1MSEC 48 +#define IRQ_DRI_DMA 49 +#define IRQ_DRI_ATTENTION 50 +#define IRQ_GPMI_ATTENTION 51 +#define IRQ_IR 52 +#define IRQ_DCP_VMI 53 +#define IRQ_DCP 54 +#define IRQ_BCH 56 +#define IRQ_PXP 57 +#define IRQ_UARTAPP2_TX_DMA 58 +#define IRQ_UARTAPP2_INTERNAL 59 +#define IRQ_UARTAPP2_RX_DMA 60 +#define IRQ_VDAC_DETECT 61 +#define IRQ_VDD5V_DROOP 64 +#define IRQ_DCDC4P2_BO 65 + + +#define NR_REAL_IRQS 128 +#define NR_IRQS (NR_REAL_IRQS + 32 * 3) +#define ARCH_NR_IRQS NR_REAL_IRQS + +/* All interrupts are FIQ capable */ +#define FIQ_START IRQ_DEBUG_UART + +/* Hard disk IRQ is a GPMI attention IRQ */ +#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-mx23/include/mach/lcdif.h b/arch/arm/mach-mx23/include/mach/lcdif.h new file mode 100644 index 000000000000..33fe188291da --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/lcdif.h @@ -0,0 +1,277 @@ +/* + * Freescale MXS LCDIF interfaces + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include <linux/types.h> +#include <linux/fb.h> +#include <linux/list.h> +#include <linux/backlight.h> +#include <linux/dma-mapping.h> +#include <linux/regulator/consumer.h> +#include <linux/platform_device.h> + +#include <mach/device.h> + +#include "regs-lcdif.h" + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct mxs_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + MXS_LCD_PANEL_SYSTEM = 0, + MXS_LCD_PANEL_VSYNC, + MXS_LCD_PANEL_DOTCLK, + MXS_LCD_PANEL_DVI, +}; + +struct mxs_platform_bl_data; +struct mxs_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device *, dma_addr_t, int, + struct mxs_platform_fb_entry *); + void (*release_panel) (struct device *, struct mxs_platform_fb_entry *); + int (*blank_panel) (int); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t); + int (*update_panel) (void *, struct mxs_platform_fb_entry *); + struct list_head link; + struct mxs_platform_bl_data *bl_data; +}; + +struct mxs_platform_fb_data { + struct list_head list; + struct mxs_platform_fb_entry *cur; + struct mxs_platform_fb_entry *next; +}; + +#define MXS_LCDIF_PANEL_INIT 1 +#define MXS_LCDIF_PANEL_RELEASE 2 + +struct mxs_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct mxs_platform_bl_data *); + int (*set_bl_intensity) (struct mxs_platform_bl_data *, + struct backlight_device *, int); + void (*free_bl) (struct mxs_platform_bl_data *); +}; + +static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_move(&pentry->link, &pdata->list); +} + +static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data + *pdata, + int (*func) (struct + mxs_platform_fb_entry + * pentry, void *data, + int ret_prev), void *data) +{ + struct mxs_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data + *pdata) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-bl", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->dev.platform_data = pdata; +} + +void mxs_init_lcdif(void); +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize); +void mxs_lcdif_dma_release(void); +void mxs_lcdif_run(void); +void mxs_lcdif_stop(void); +int mxs_lcdif_pan_display(dma_addr_t addr); + +int mxs_lcdif_register_client(struct notifier_block *nb); +void mxs_lcdif_unregister_client(struct notifier_block *nb); +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + /* vsync is output */ + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx23/include/mach/mx23.h b/arch/arm/mach-mx23/include/mach/mx23.h new file mode 100644 index 000000000000..c9f6fd29bf78 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/mx23.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX23_H___ +#define __ASM_ARCH_MACH_MX23_H___ + +#include <asm/sizes.h> +#include <mach/irqs.h> + +#define MX23_SOC_IO_PHYS_BASE 0x80000000 +#define MX23_SOC_IO_VIRT_BASE 0xF0000000 +#define MX23_SOC_IO_AREA_SIZE SZ_1M + +#define ICOLL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x000000) +#define APBH_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x004000) +#define BCH_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x010000) +#define SSP2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x034000) +#define PINCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x020000) +#define APBX_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x030000) +#define CLKCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x046000) +#define LRADC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x05c000) +#define I2C0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x058000) +#define PWM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x068000) +#define AUART1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06E000) +#define DUART_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x070000) +#define USBPHY_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x07C000) +#define USBCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x080000) +#define DRAM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x0E0000) + +#define MX23_SOC_IO_ADDRESS(x) \ + ((x) - MX23_SOC_IO_PHYS_BASE + MX23_SOC_IO_VIRT_BASE) + +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX23_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX23_SOC_IO_PHYS_BASE + \ + MX23_SOC_IO_AREA_SIZE) ? \ + MX23_SOC_IO_ADDRESS(x) : 0xDEADBEEF) + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif + +#ifdef CONFIG_DEBUG_LL +#define MXS_LL_UART_PADDR DUART_PHYS_ADDR +#define MXS_LL_UART_VADDR MX23_SOC_IO_ADDRESS(DUART_PHYS_ADDR) +#endif +#endif /* __ASM_ARCH_MACH_MX23_H__ */ diff --git a/arch/arm/mach-mx23/include/mach/regs-i2c.h b/arch/arm/mach-mx23/include/mach/regs-i2c.h new file mode 100644 index 000000000000..a255d3fa78c5 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-i2c.h @@ -0,0 +1,383 @@ +/* + * Freescale I2C Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.54 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H + + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) + +#define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD1 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_PIO_MODE 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) + +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) + +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) + +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) + +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) + +#define BP_I2C_CTRL1_RSVD1 29 +#define BM_I2C_CTRL1_RSVD1 0xE0000000 +#define BF_I2C_CTRL1_RSVD1(v) \ + (((v) << 29) & BM_I2C_CTRL1_RSVD1) +#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_DATA (0x00000060) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x00000070) +#define HW_I2C_DEBUG0_SET (0x00000074) +#define HW_I2C_DEBUG0_CLR (0x00000078) +#define HW_I2C_DEBUG0_TOG (0x0000007c) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_TBD 26 +#define BM_I2C_DEBUG0_TBD 0x0C000000 +#define BF_I2C_DEBUG0_TBD(v) \ + (((v) << 26) & BM_I2C_DEBUG0_TBD) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_TESTMODE 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x00000080) +#define HW_I2C_DEBUG1_SET (0x00000084) +#define HW_I2C_DEBUG1_CLR (0x00000088) +#define HW_I2C_DEBUG1_TOG (0x0000008c) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x00000090) + +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-lcdif.h b/arch/arm/mach-mx23/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..b8eae0f47e57 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-lcdif.h @@ -0,0 +1,650 @@ +/* + * Freescale LCDIF Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H + + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) + +#define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_RSRVD0 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_DMA_BURST_LENGTH 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 + +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) + +#define BP_LCDIF_CTRL1_RSRVD1 27 +#define BM_LCDIF_CTRL1_RSRVD1 0xF8000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 27) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RSRVD0 0x00000080 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER 0x00000040 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 0x00000020 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 0x00000010 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x00000008 +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000020) + +#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_LCDIF_CUR_BUF (0x00000030) + +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_LCDIF_NEXT_BUF (0x00000040) + +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_PAGETABLE (0x00000050) + +#define BP_LCDIF_PAGETABLE_BASE 14 +#define BM_LCDIF_PAGETABLE_BASE 0xFFFFC000 +#define BF_LCDIF_PAGETABLE_BASE(v) \ + (((v) << 14) & BM_LCDIF_PAGETABLE_BASE) +#define BP_LCDIF_PAGETABLE_RSVD1 2 +#define BM_LCDIF_PAGETABLE_RSVD1 0x00003FFC +#define BF_LCDIF_PAGETABLE_RSVD1(v) \ + (((v) << 2) & BM_LCDIF_PAGETABLE_RSVD1) +#define BM_LCDIF_PAGETABLE_FLUSH 0x00000002 +#define BM_LCDIF_PAGETABLE_ENABLE 0x00000001 + +#define HW_LCDIF_TIMING (0x00000060) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) +#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) + +#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) + +#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 24) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_RSRVD0 18 +#define BM_LCDIF_VDCTRL2_RSRVD0 0x00FC0000 +#define BF_LCDIF_VDCTRL2_RSRVD0(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_RSRVD0) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_LCDIF_VDCTRL3 (0x000000a0) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_LCDIF_VDCTRL4 (0x000000b0) + +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0xFFF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) +#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_LCDIF_DVICTRL0 (0x000000c0) + +#define BM_LCDIF_DVICTRL0_START_TRS 0x80000000 +#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) +#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_V_LINES_CNT) + +#define HW_LCDIF_DVICTRL1 (0x000000d0) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) +#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) + +#define HW_LCDIF_DVICTRL2 (0x000000e0) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) +#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL3 (0x000000f0) + +#define BP_LCDIF_DVICTRL3_RSRVD1 26 +#define BM_LCDIF_DVICTRL3_RSRVD1 0xFC000000 +#define BF_LCDIF_DVICTRL3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_DVICTRL3_RSRVD1) +#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_RSRVD0 10 +#define BM_LCDIF_DVICTRL3_RSRVD0 0x0000FC00 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL4 (0x00000100) + +#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_LCDIF_CSC_COEFF0 (0x00000110) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) +#define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_LCDIF_CSC_COEFF1 (0x00000120) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) +#define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) + +#define HW_LCDIF_CSC_COEFF2 (0x00000130) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) +#define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) + +#define HW_LCDIF_CSC_COEFF3 (0x00000140) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) +#define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) + +#define HW_LCDIF_CSC_COEFF4 (0x00000150) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) +#define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) + +#define HW_LCDIF_CSC_OFFSET (0x00000160) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) +#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) + +#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_PIN_SHARING_CTRL0 (0x00000180) +#define HW_LCDIF_PIN_SHARING_CTRL0_SET (0x00000184) +#define HW_LCDIF_PIN_SHARING_CTRL0_CLR (0x00000188) +#define HW_LCDIF_PIN_SHARING_CTRL0_TOG (0x0000018c) + +#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1 6 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1 0xFFFFFFC0 +#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v) \ + (((v) << 6) & BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1) +#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 4 +#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 0x00000030 +#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v) \ + (((v) << 4) & BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE) +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD 0x1 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL 0x2 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL 0x3 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0 0x00000008 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 0x00000004 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 0x00000002 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST 0x1 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0x00000001 + +#define HW_LCDIF_PIN_SHARING_CTRL1 (0x00000190) + +#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0 +#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v) (v) + +#define HW_LCDIF_PIN_SHARING_CTRL2 (0x000001a0) + +#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0 +#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v) (v) + +#define HW_LCDIF_DATA (0x000001b0) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x000001c0) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_STAT (0x000001d0) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 0 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFFFF +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_STAT_RSRVD0) + +#define HW_LCDIF_VERSION (0x000001e0) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001f0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ 0x00000800 +#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 0x00000400 +#define BP_LCDIF_DEBUG0_RSRVD0 0 +#define BM_LCDIF_DEBUG0_RSRVD0 0x000003FF +#define BF_LCDIF_DEBUG0_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_RSRVD0) + +#define HW_LCDIF_DEBUG1 (0x00000200) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-lradc.h b/arch/arm/mach-mx23/include/mach/regs-lradc.h new file mode 100644 index 000000000000..77af4be1d33b --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-lradc.h @@ -0,0 +1,669 @@ +/* + * Freescale LRADC Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H + + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) + +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 22 +#define BM_LRADC_CTRL0_RSRVD2 0x3FC00000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 22) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) + +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) + +#define BP_LRADC_CTRL1_RSRVD2 25 +#define BM_LRADC_CTRL1_RSRVD2 0xFE000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 25) & BM_LRADC_CTRL1_RSRVD2) +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 9 +#define BM_LRADC_CTRL1_RSRVD1 0x0000FE00 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 9) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) + +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x00800000 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 +#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 +#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 +#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 +#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 +#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) \ + (((v) << 16) & BM_LRADC_CTRL2_BL_BRIGHTNESS) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BM_LRADC_CTRL2_RSRVD1 0x00004000 +#define BM_LRADC_CTRL2_EXT_EN1 0x00002000 +#define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 +#define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 +#define BM_LRADC_CTRL2_EXT_EN0 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 + +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 + +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) + +#define BP_LRADC_STATUS_RSRVD3 27 +#define BM_LRADC_STATUS_RSRVD3 0xF8000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 27) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 1 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFFE +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 1) & BM_LRADC_STATUS_RSRVD2) +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) + +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) + +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) + +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_VERSION (0x00000150) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-pwm.h b/arch/arm/mach-mx23/include/mach/regs-pwm.h new file mode 100644 index 000000000000..30380d71e2e4 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-pwm.h @@ -0,0 +1,135 @@ +/* + * Freescale PWM Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.23 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H + + +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) + +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x02000000 +#define BP_PWM_CTRL_RSRVD1 7 +#define BM_PWM_CTRL_RSRVD1 0x01FFFF80 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 7) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000040 +#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 5 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 5 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_PWM_PERIODn_RSRVD2 25 +#define BM_PWM_PERIODn_RSRVD2 0xFE000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 25) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 +#define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x000000b0) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-rtc.h b/arch/arm/mach-mx23/include/mach/regs-rtc.h new file mode 100644 index 000000000000..a953a1d361ca --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-rtc.h @@ -0,0 +1,219 @@ +/* + * Freescale RTC Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.75 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H + + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 +#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) + +#define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) + +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) + +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) + +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) + +#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 18) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) + +#define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) + +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-ssp.h b/arch/arm/mach-mx23/include/mach/regs-ssp.h new file mode 100644 index 000000000000..cdc07f8930dd --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-ssp.h @@ -0,0 +1,392 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 2.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_XFER_COUNT 0 +#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_SSP_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_SSP_CTRL0_XFER_COUNT) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 23 +#define BM_SSP_CMD0_RSVD0 0xFF800000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 23) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_BLOCK_SIZE 16 +#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 +#define BF_SSP_CMD0_BLOCK_SIZE(v) \ + (((v) << 16) & BM_SSP_CMD0_BLOCK_SIZE) +#define BP_SSP_CMD0_BLOCK_COUNT 8 +#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 +#define BF_SSP_CMD0_BLOCK_COUNT(v) \ + (((v) << 8) & BM_SSP_CMD0_BLOCK_COUNT) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_COMPREF (0x00000030) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000040) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000050) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000060) +#define HW_SSP_CTRL1_SET (0x00000064) +#define HW_SSP_CTRL1_CLR (0x00000068) +#define HW_SSP_CTRL1_TOG (0x0000006c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 +#define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 + +#define HW_SSP_DATA (0x00000070) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x00000080) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x00000090) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000a0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000b0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_STATUS (0x000000c0) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 22 +#define BM_SSP_STATUS_RSVD3 0x0FC00000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 22) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DEBUG (0x00000100) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000110) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-timrot.h b/arch/arm/mach-mx23/include/mach/regs-timrot.h new file mode 100644 index 000000000000..860709e92941 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-timrot.h @@ -0,0 +1,257 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.38 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BM_TIMROT_ROTCTRL_RSRVD2 0x00000080 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 +#define BM_TIMROT_ROTCTRL_RSRVD1 0x00000008 +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_TIMROT_TIMCTRLn_RSRVD2 16 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00003E00 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC + +/* + * multi-register-define name HW_TIMROT_TIMCOUNTn + * base 0x00000030 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCOUNTn(n) (0x00000030 + (n) * 0x20) +#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT) + +#define HW_TIMROT_TIMCTRL3 (0x00000080) +#define HW_TIMROT_TIMCTRL3_SET (0x00000084) +#define HW_TIMROT_TIMCTRL3_CLR (0x00000088) +#define HW_TIMROT_TIMCTRL3_TOG (0x0000008c) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 11 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003800 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 11) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC + +#define HW_TIMROT_TIMCOUNT3 (0x00000090) + +#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT) + +#define HW_TIMROT_VERSION (0x000000a0) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx23/include/mach/regulator.h b/arch/arm/mach-mx23/include/mach/regulator.h new file mode 100644 index 000000000000..1b073586268b --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regulator.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __PLAT_REGULATOR_H_ +#define __PLAT_REGULATOR_H_ + +#define MXS_REG5V_NOT_USB 0 +#define MXS_REG5V_IS_USB 1 +#define MXS_VDDD 0 +#define MXS_VDDA 1 +#define MXS_VDDIO 2 +#define MXS_VDDDBO 3 +#define MXS_OVERALL_CUR 4 + +#endif diff --git a/arch/arm/mach-mx23/mx23_pins.h b/arch/arm/mach-mx23/mx23_pins.h new file mode 100644 index 000000000000..a87ab9d6fc81 --- /dev/null +++ b/arch/arm/mach-mx23/mx23_pins.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +#include <mach/pinctrl.h> + +/* + * Define MX28 pins, the pin name corresponds to MX28 hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0) +#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1) +#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2) +#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3) +#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4) +#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5) +#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6) +#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7) +#define PINID_GPMI_CE0N MXS_PIN_ENCODE(0, 16) +#define PINID_GPMI_CE1N MXS_PIN_ENCODE(0, 17) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_CE3N MXS_PIN_ENCODE(0, 19) +#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 20) +#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 21) +#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 22) +#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 23) +#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 24) +#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 25) +#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 26) +#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 27) +#define PINID_GPMI_RESETN MXS_PIN_ENCODE(0, 28) + +/* Bank 1 */ +#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0) +#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1) +#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2) +#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3) +#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4) +#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5) +#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6) +#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7) +#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8) +#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9) +#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10) +#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11) +#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12) +#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13) +#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14) +#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15) +#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16) +#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17) +#define PINID_LCD_D18 MXS_PIN_ENCODE(1, 18) +#define PINID_LCD_D19 MXS_PIN_ENCODE(1, 19) +#define PINID_LCD_D20 MXS_PIN_ENCODE(1, 20) +#define PINID_LCD_D21 MXS_PIN_ENCODE(1, 21) +#define PINID_LCD_D22 MXS_PIN_ENCODE(1, 22) +#define PINID_LCD_D23 MXS_PIN_ENCODE(1, 23) +#define PINID_LCD_RD_E MXS_PIN_ENCODE(1, 24) +#define PINID_LCD_WR_RWN MXS_PIN_ENCODE(1, 25) +#define PINID_LCD_RS MXS_PIN_ENCODE(1, 26) +#define PINID_LCD_CS MXS_PIN_ENCODE(1, 27) +#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 28) +#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 29) +#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 30) +#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 31) + +/* Bank 2 */ +#define PINID_SSP0_DATA0 MXS_PIN_ENCODE(2, 0) +#define PINID_SSP0_DATA1 MXS_PIN_ENCODE(2, 1) +#define PINID_SSP0_DATA2 MXS_PIN_ENCODE(2, 2) +#define PINID_SSP0_DATA3 MXS_PIN_ENCODE(2, 3) +#define PINID_SSP0_DATA4 MXS_PIN_ENCODE(2, 4) +#define PINID_SSP0_DATA5 MXS_PIN_ENCODE(2, 5) +#define PINID_SSP0_DATA6 MXS_PIN_ENCODE(2, 6) +#define PINID_SSP0_DATA7 MXS_PIN_ENCODE(2, 7) +#define PINID_SSP0_CMD MXS_PIN_ENCODE(2, 8) +#define PINID_SSP0_DETECT MXS_PIN_ENCODE(2, 9) +#define PINID_SSP0_SCK MXS_PIN_ENCODE(2, 10) +#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 12) +#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 13) +#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 14) +#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 15) +#define PINID_SSP2_SCK MXS_PIN_ENCODE(2, 16) +#define PINID_SSP2_MOSI MXS_PIN_ENCODE(2, 17) +#define PINID_SSP2_MISO MXS_PIN_ENCODE(2, 18) +#define PINID_SSP2_SS0 MXS_PIN_ENCODE(2, 19) +#define PINID_SSP2_SS1 MXS_PIN_ENCODE(2, 20) +#define PINID_SSP2_SS2 MXS_PIN_ENCODE(2, 21) +#define PINID_SSP3_SCK MXS_PIN_ENCODE(2, 24) +#define PINID_SSP3_MOSI MXS_PIN_ENCODE(2, 25) +#define PINID_SSP3_MISO MXS_PIN_ENCODE(2, 26) +#define PINID_SSP3_SS0 MXS_PIN_ENCODE(2, 27) + +/* Bank 3 */ +#define PINID_AUART0_RX MXS_PIN_ENCODE(3, 0) +#define PINID_AUART0_TX MXS_PIN_ENCODE(3, 1) +#define PINID_AUART0_CTS MXS_PIN_ENCODE(3, 2) +#define PINID_AUART0_RTS MXS_PIN_ENCODE(3, 3) +#define PINID_AUART1_RX MXS_PIN_ENCODE(3, 4) +#define PINID_AUART1_TX MXS_PIN_ENCODE(3, 5) +#define PINID_AUART1_CTS MXS_PIN_ENCODE(3, 6) +#define PINID_AUART1_RTS MXS_PIN_ENCODE(3, 7) +#define PINID_AUART2_RX MXS_PIN_ENCODE(3, 8) +#define PINID_AUART2_TX MXS_PIN_ENCODE(3, 9) +#define PINID_AUART2_CTS MXS_PIN_ENCODE(3, 10) +#define PINID_AUART2_RTS MXS_PIN_ENCODE(3, 11) +#define PINID_AUART3_RX MXS_PIN_ENCODE(3, 12) +#define PINID_AUART3_TX MXS_PIN_ENCODE(3, 13) +#define PINID_AUART3_CTS MXS_PIN_ENCODE(3, 14) +#define PINID_AUART3_RTS MXS_PIN_ENCODE(3, 15) +#define PINID_PWM0 MXS_PIN_ENCODE(3, 16) +#define PINID_PWM1 MXS_PIN_ENCODE(3, 17) +#define PINID_PWM2 MXS_PIN_ENCODE(3, 18) +#define PINID_SAIF0_MCLK MXS_PIN_ENCODE(3, 20) +#define PINID_SAIF0_LRCLK MXS_PIN_ENCODE(3, 21) +#define PINID_SAIF0_BITCLK MXS_PIN_ENCODE(3, 22) +#define PINID_SAIF0_SDATA0 MXS_PIN_ENCODE(3, 23) +#define PINID_I2C0_SCL MXS_PIN_ENCODE(3, 24) +#define PINID_I2C0_SDA MXS_PIN_ENCODE(3, 25) +#define PINID_SAIF1_SDATA0 MXS_PIN_ENCODE(3, 26) +#define PINID_SPDIF MXS_PIN_ENCODE(3, 27) +#define PINID_PWM3 MXS_PIN_ENCODE(3, 28) +#define PINID_PWM4 MXS_PIN_ENCODE(3, 29) +#define PINID_LCD_RESET MXS_PIN_ENCODE(3, 30) + +/* Bank 4 */ +#define PINID_ENET0_MDC MXS_PIN_ENCODE(4, 0) +#define PINID_ENET0_MDIO MXS_PIN_ENCODE(4, 1) +#define PINID_ENET0_RX_EN MXS_PIN_ENCODE(4, 2) +#define PINID_ENET0_RXD0 MXS_PIN_ENCODE(4, 3) +#define PINID_ENET0_RXD1 MXS_PIN_ENCODE(4, 4) +#define PINID_ENET0_TX_CLK MXS_PIN_ENCODE(4, 5) +#define PINID_ENET0_TX_EN MXS_PIN_ENCODE(4, 6) +#define PINID_ENET0_TXD0 MXS_PIN_ENCODE(4, 7) +#define PINID_ENET0_TXD1 MXS_PIN_ENCODE(4, 8) +#define PINID_ENET0_RXD2 MXS_PIN_ENCODE(4, 9) +#define PINID_ENET0_RXD3 MXS_PIN_ENCODE(4, 10) +#define PINID_ENET0_TXD2 MXS_PIN_ENCODE(4, 11) +#define PINID_ENET0_TXD3 MXS_PIN_ENCODE(4, 12) +#define PINID_ENET0_RX_CLK MXS_PIN_ENCODE(4, 13) +#define PINID_ENET0_COL MXS_PIN_ENCODE(4, 14) +#define PINID_ENET0_CRS MXS_PIN_ENCODE(4, 15) +#define PINID_ENET_CLK MXS_PIN_ENCODE(4, 16) +#define PINID_JTAG_RTCK MXS_PIN_ENCODE(4, 20) +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-mx23/mx23evk.c b/arch/arm/mach-mx23/mx23evk.c new file mode 100644 index 000000000000..8f4f5888afa1 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/pinctrl.h> + +#include "device.h" +#include "mx23evk.h" + +static void __init fixup_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mx23_set_input_clk(24000000, 24000000, 32000, 50000000); +} + +static void __init mx23evk_device_init(void) +{ + /* Add mx23evk special code */ +} + +static void __init mx23evk_init_machine(void) +{ +#if 0 + mx23_pinctrl_init(); + mx23_gpio_init(); + mx23evk_pins_init(); +#endif + mx23_device_init(); + mx23evk_device_init(); +} + +MACHINE_START(MX23EVK, "Freescale MX23EVK board") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .fixup = fixup_board, + .map_io = mx23_map_io, + .init_irq = mx23_irq_init, + .init_machine = mx23evk_init_machine, + .timer = &mx23_timer.timer, +MACHINE_END diff --git a/arch/arm/mach-mx23/mx23evk.h b/arch/arm/mach-mx23/mx23evk.h new file mode 100644 index 000000000000..619ade49ecb1 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_MACH_MX23EVK_H +#define __ASM_ARM_MACH_MX23EVK_H + +extern void __init mx23evk_pins_init(void); +#endif /* __ASM_ARM_MACH_MX28EVK_H */ diff --git a/arch/arm/mach-mx23/mx23evk_pins.c b/arch/arm/mach-mx23/mx23evk_pins.c new file mode 100644 index 000000000000..1c105d8ced27 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk_pins.c @@ -0,0 +1,722 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/gpio.h> + +#include <mach/pinctrl.h> + +#include "mx23_pins.h" + +static struct pin_desc mx23evk_fixed_pins[] = { + { + .name = "DUART.RX", + .id = PINID_PWM0, + .fun = PIN_FUN3, + }, + { + .name = "DUART.TX", + .id = PINID_PWM1, + .fun = PIN_FUN3, + }, +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + { + .name = "AUART0.RX", + .id = PINID_AUART0_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.TX", + .id = PINID_AUART0_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.CTS", + .id = PINID_AUART0_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.RTS", + .id = PINID_AUART0_RTS, + .fun = PIN_FUN1, + }, +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + { + .name = "AUART3.RX", + .id = PINID_AUART3_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.TX", + .id = PINID_AUART3_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.CTS", + .id = PINID_AUART3_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.RTS", + .id = PINID_AUART3_RTS, + .fun = PIN_FUN1, + }, +#endif + { + .name = "usb0", + .id = PINID_AUART2_TX, + .fun = PIN_GPIO, + .data = 1, + }, + { + .name = "usb1", + .id = PINID_AUART2_RX, + .fun = PIN_GPIO, + .data = 1, + }, + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) + { + .name = "I2C0_SCL", + .id = PINID_I2C0_SCL, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "I2C0_SDA", + .id = PINID_I2C0_SDA, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) + { + .name = "LCD_D00", + .id = PINID_LCD_D00, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D01", + .id = PINID_LCD_D01, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D02", + .id = PINID_LCD_D02, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D03", + .id = PINID_LCD_D03, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D04", + .id = PINID_LCD_D04, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D05", + .id = PINID_LCD_D05, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D06", + .id = PINID_LCD_D06, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D07", + .id = PINID_LCD_D07, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D08", + .id = PINID_LCD_D08, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D09", + .id = PINID_LCD_D09, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D10", + .id = PINID_LCD_D10, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D11", + .id = PINID_LCD_D11, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D12", + .id = PINID_LCD_D12, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D13", + .id = PINID_LCD_D13, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D14", + .id = PINID_LCD_D14, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D15", + .id = PINID_LCD_D15, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D16", + .id = PINID_LCD_D16, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D17", + .id = PINID_LCD_D17, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D18", + .id = PINID_LCD_D18, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D19", + .id = PINID_LCD_D19, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D20", + .id = PINID_LCD_D20, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D21", + .id = PINID_LCD_D21, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D22", + .id = PINID_LCD_D22, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D23", + .id = PINID_LCD_D23, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_RESET", + .id = PINID_LCD_RESET, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_VSYNC", + .id = PINID_LCD_RD_E, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_HSYNC", + .id = PINID_LCD_WR_RWN, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_ENABLE", + .id = PINID_LCD_CS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_DOTCLK", + .id = PINID_LCD_RS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_BACKLIGHT", + .id = PINID_PWM2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) + /* Configurations of SSP0 SD/MMC port pins */ + { + .name = "SSP0_DATA0", + .id = PINID_SSP0_DATA0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA1", + .id = PINID_SSP0_DATA1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA2", + .id = PINID_SSP0_DATA2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA3", + .id = PINID_SSP0_DATA3, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA4", + .id = PINID_SSP0_DATA4, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA5", + .id = PINID_SSP0_DATA5, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA6", + .id = PINID_SSP0_DATA6, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA7", + .id = PINID_SSP0_DATA7, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_CMD", + .id = PINID_SSP0_CMD, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DETECT", + .id = PINID_SSP0_DETECT, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP0_SCK", + .id = PINID_SSP0_SCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + /* Configurations of SSP1 SD/MMC port pins */ + { + .name = "SSP1_DATA0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DETECT", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP1_SCK", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) + { + .name = "ENET0_MDC", + .id = PINID_ENET0_MDC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_MDIO", + .id = PINID_ENET0_MDIO, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RX_EN", + .id = PINID_ENET0_RX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD0", + .id = PINID_ENET0_RXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD1", + .id = PINID_ENET0_RXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TX_EN", + .id = PINID_ENET0_TX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD0", + .id = PINID_ENET0_TXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD1", + .id = PINID_ENET0_TXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET_CLK", + .id = PINID_ENET_CLK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +}; + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +int mx23evk_enet_gpio_init(void) +{ + /* pwr */ + gpio_request(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), "ENET_PWR"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + + /* reset phy */ + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + + return 0; +} +#else +int mx23evk_enet_gpio_init(void) +{ + return 0; +} +#endif + +void __init mx23evk_pins_init(void) +{ + int i; + struct pin_desc *pin; + for (i = 0; i < ARRAY_SIZE(mx23evk_fixed_pins); i++) { + pin = &mx23evk_fixed_pins[i]; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->input) + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + else + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + } + } +} diff --git a/arch/arm/mach-mx23/pinctrl.c b/arch/arm/mach-mx23/pinctrl.c new file mode 100644 index 000000000000..0cb85e2674ef --- /dev/null +++ b/arch/arm/mach-mx23/pinctrl.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/pinctrl.h> + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx23_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id) +{ + int bank; + bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK); + if (bank == MXS_PIN_BANK_MAX) + return -EINVAL; + *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK); + return bank; +} + +static unsigned int mx23_get_gpio(struct pin_bank *bank, unsigned int id) +{ + if (bank->gpio_port >= MXS_NON_GPIO) + return -EINVAL; + return bank->gpio_port * PINS_PER_BANK + id; +} + +static void mx23_set_strength(struct pin_bank *bank, + unsigned int id, enum pad_strength strength) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id *= 4; + __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER); + __raw_writel(strength << id, addr + SET_REGISTER); +} + +static void mx23_set_voltage(struct pin_bank *bank, + unsigned int id, enum pad_voltage volt) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id = id * 4 + 2; + if (volt == PAD_1_8V) + __raw_writel(1 << id, addr + CLR_REGISTER); + else + __raw_writel(1 << id, addr + SET_REGISTER); +} + +static void mx23_set_pullup(struct pin_bank *bank, unsigned int id, int pullup) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0; + addr += 0x10 * bank->id; + if (pullup) + __raw_writel(1 << id, addr + SET_REGISTER); + else + __raw_writel(1 << id, addr + CLR_REGISTER); +} + +static void mx23_set_type(struct pin_bank *bank, + unsigned int id, enum pin_fun cfg) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + __raw_writel(0x3 << id, addr + CLR_REGISTER); + __raw_writel(cfg << id, addr + SET_REGISTER); +} + +static struct pin_bank mx23_pin_banks[6] = { + [0] = { + .id = 0, + .gpio_port = 0, + }, + [1] = { + .id = 1, + .gpio_port = 1, + }, + [2] = { + .id = 2, + .gpio_port = 2, + }, + [3] = { + .id = 3, + .gpio_port = 3, + }, + [4] = { + .id = 4, + .gpio_port = 4, + }, + [5] = { + .id = 5, + .gpio_port = MXS_NON_GPIO, + } +}; + +static struct pinctrl_chip mx23_pinctrl = { + .name = "pinctrl", + .banks = mx23_pin_banks, + .pin2id = mx23_pin2id, + .get_gpio = mx23_get_gpio, + .set_strength = mx23_set_strength, + .set_voltage = mx23_set_voltage, + .set_pullup = mx23_set_pullup, + .set_type = mx23_set_type, +}; + +int __init mx23_pinctrl_init(void) +{ + int i; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + mx23_pinctrl.bank_size = ARRAY_SIZE(mx23_pin_banks); + return mxs_set_pinctrl_chip(&mx23_pinctrl); +} diff --git a/arch/arm/mach-mx23/regs-clkctrl.h b/arch/arm/mach-mx23/regs-clkctrl.h new file mode 100644 index 000000000000..7b8e089f9707 --- /dev/null +++ b/arch/arm/mach-mx23/regs-clkctrl.h @@ -0,0 +1,442 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + + +#define HW_CLKCTRL_PLLCTRL0 (0x00000000) +#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 +#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) + +#define HW_CLKCTRL_PLLCTRL1 (0x00000010) + +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_CPU (0x00000020) +#define HW_CLKCTRL_CPU_SET (0x00000024) +#define HW_CLKCTRL_CPU_CLR (0x00000028) +#define HW_CLKCTRL_CPU_TOG (0x0000002c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000030) +#define HW_CLKCTRL_HBUS_SET (0x00000034) +#define HW_CLKCTRL_HBUS_CLR (0x00000038) +#define HW_CLKCTRL_HBUS_TOG (0x0000003c) + +#define BP_CLKCTRL_HBUS_RSRVD4 30 +#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 +#define BF_CLKCTRL_HBUS_RSRVD4(v) \ + (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000040) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 11 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000050) +#define HW_CLKCTRL_XTAL_SET (0x00000054) +#define HW_CLKCTRL_XTAL_CLR (0x00000058) +#define HW_CLKCTRL_XTAL_TOG (0x0000005c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_PIX (0x00000060) + +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BP_CLKCTRL_PIX_RSRVD1 13 +#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 +#define BF_CLKCTRL_PIX_RSRVD1(v) \ + (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0x00000FFF +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_PIX_DIV) + +#define HW_CLKCTRL_SSP (0x00000070) + +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BP_CLKCTRL_SSP_RSRVD1 10 +#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BF_CLKCTRL_SSP_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP_DIV) + +#define HW_CLKCTRL_GPMI (0x00000080) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x00000090) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000a0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_IR (0x000000b0) + +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BM_CLKCTRL_IR_RSRVD3 0x40000000 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 +#define BP_CLKCTRL_IR_RSRVD2 25 +#define BM_CLKCTRL_IR_RSRVD2 0x06000000 +#define BF_CLKCTRL_IR_RSRVD2(v) \ + (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) +#define BP_CLKCTRL_IR_RSRVD1 10 +#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 +#define BF_CLKCTRL_IR_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x000003FF +#define BF_CLKCTRL_IR_IR_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) + +#define HW_CLKCTRL_SAIF (0x000000c0) + +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF_RSRVD1 17 +#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF_DIV) + +#define HW_CLKCTRL_TV (0x000000d0) + +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +#define BP_CLKCTRL_TV_RSRVD 0 +#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_TV_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_TV_RSRVD) + +#define HW_CLKCTRL_ETM (0x000000e0) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 7 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000003F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_FRAC (0x000000f0) +#define HW_CLKCTRL_FRAC_SET (0x000000f4) +#define HW_CLKCTRL_FRAC_CLR (0x000000f8) +#define HW_CLKCTRL_FRAC_TOG (0x000000fc) + +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x00000100) +#define HW_CLKCTRL_FRAC1_SET (0x00000104) +#define HW_CLKCTRL_FRAC1_CLR (0x00000108) +#define HW_CLKCTRL_FRAC1_TOG (0x0000010c) + +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC1_RSRVD1 0 +#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF +#define BF_CLKCTRL_FRAC1_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) + +#define HW_CLKCTRL_CLKSEQ (0x00000110) +#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) +#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) +#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) + +#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 + +#define HW_CLKCTRL_RESET (0x00000120) + +#define BP_CLKCTRL_RESET_RSRVD 2 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x00000130) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000140) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-mx23/regs-digctl.h b/arch/arm/mach-mx23/regs-digctl.h new file mode 100644 index 000000000000..291ba927f63a --- /dev/null +++ b/arch/arm/mach-mx23/regs-digctl.h @@ -0,0 +1,724 @@ +/* + * Freescale DIGCTL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___DIGCTL_H +#define __ARCH_ARM___DIGCTL_H + + +#define HW_DIGCTL_CTRL (0x00000000) +#define HW_DIGCTL_CTRL_SET (0x00000004) +#define HW_DIGCTL_CTRL_CLR (0x00000008) +#define HW_DIGCTL_CTRL_TOG (0x0000000c) + +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 +#define BP_DIGCTL_CTRL_RSVD2 27 +#define BM_DIGCTL_CTRL_RSVD2 0x18000000 +#define BF_DIGCTL_CTRL_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_CTRL_RSVD2) +#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x04000000 +#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x02000000 +#define BM_DIGCTL_CTRL_LCD_BIST_START 0x01000000 +#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x00800000 +#define BM_DIGCTL_CTRL_DCP_BIST_START 0x00400000 +#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x00200000 +#define BM_DIGCTL_CTRL_USB_TESTMODE 0x00100000 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00080000 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00040000 +#define BM_DIGCTL_CTRL_ARM_BIST_START 0x00020000 +#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x00010000 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00006000 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \ + (((v) << 13) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL) +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 +#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x00001000 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 +#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x00000800 +#define BM_DIGCTL_CTRL_RSVD1 0x00000400 +#define BM_DIGCTL_CTRL_SY_ENDIAN 0x00000200 +#define BM_DIGCTL_CTRL_SY_SFTRST 0x00000100 +#define BM_DIGCTL_CTRL_SY_CLKGATE 0x00000080 +#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x00000040 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 +#define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x00000020 +#define BM_DIGCTL_CTRL_TRAP_ENABLE 0x00000010 +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008 +#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 +#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001 + +#define HW_DIGCTL_STATUS (0x00000010) +#define HW_DIGCTL_STATUS_SET (0x00000014) +#define HW_DIGCTL_STATUS_CLR (0x00000018) +#define HW_DIGCTL_STATUS_TOG (0x0000001c) + +#define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 +#define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 +#define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 +#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 +#define BP_DIGCTL_STATUS_RSVD2 11 +#define BM_DIGCTL_STATUS_RSVD2 0x0FFFF800 +#define BF_DIGCTL_STATUS_RSVD2(v) \ + (((v) << 11) & BM_DIGCTL_STATUS_RSVD2) +#define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x00000400 +#define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x00000200 +#define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x00000100 +#define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x00000080 +#define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x00000040 +#define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x00000020 +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010 +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \ + (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE) +#define BM_DIGCTL_STATUS_WRITTEN 0x00000001 + +#define HW_DIGCTL_HCLKCOUNT (0x00000020) +#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024) +#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028) +#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c) + +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v) + +#define HW_DIGCTL_RAMCTRL (0x00000030) +#define HW_DIGCTL_RAMCTRL_SET (0x00000034) +#define HW_DIGCTL_RAMCTRL_CLR (0x00000038) +#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c) + +#define BP_DIGCTL_RAMCTRL_RSVD1 12 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFFF000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_RAMCTRL_RSVD1) +#define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 +#define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0x00000F00 +#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_RAMCTRL_SPEED_SELECT) +#define BP_DIGCTL_RAMCTRL_RSVD0 1 +#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FE +#define BF_DIGCTL_RAMCTRL_RSVD0(v) \ + (((v) << 1) & BM_DIGCTL_RAMCTRL_RSVD0) +#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x00000001 + +#define HW_DIGCTL_RAMREPAIR (0x00000040) +#define HW_DIGCTL_RAMREPAIR_SET (0x00000044) +#define HW_DIGCTL_RAMREPAIR_CLR (0x00000048) +#define HW_DIGCTL_RAMREPAIR_TOG (0x0000004c) + +#define BP_DIGCTL_RAMREPAIR_RSVD1 16 +#define BM_DIGCTL_RAMREPAIR_RSVD1 0xFFFF0000 +#define BF_DIGCTL_RAMREPAIR_RSVD1(v) \ + (((v) << 16) & BM_DIGCTL_RAMREPAIR_RSVD1) +#define BP_DIGCTL_RAMREPAIR_ADDR 0 +#define BM_DIGCTL_RAMREPAIR_ADDR 0x0000FFFF +#define BF_DIGCTL_RAMREPAIR_ADDR(v) \ + (((v) << 0) & BM_DIGCTL_RAMREPAIR_ADDR) + +#define HW_DIGCTL_ROMCTRL (0x00000050) +#define HW_DIGCTL_ROMCTRL_SET (0x00000054) +#define HW_DIGCTL_ROMCTRL_CLR (0x00000058) +#define HW_DIGCTL_ROMCTRL_TOG (0x0000005c) + +#define BP_DIGCTL_ROMCTRL_RSVD0 4 +#define BM_DIGCTL_ROMCTRL_RSVD0 0xFFFFFFF0 +#define BF_DIGCTL_ROMCTRL_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_ROMCTRL_RSVD0) +#define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 +#define BM_DIGCTL_ROMCTRL_RD_MARGIN 0x0000000F +#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) \ + (((v) << 0) & BM_DIGCTL_ROMCTRL_RD_MARGIN) + +#define HW_DIGCTL_WRITEONCE (0x00000060) + +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF +#define BF_DIGCTL_WRITEONCE_BITS(v) (v) + +#define HW_DIGCTL_ENTROPY (0x00000090) + +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_VALUE(v) (v) + +#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0) + +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v) + +#define HW_DIGCTL_SJTAGDBG (0x000000b0) +#define HW_DIGCTL_SJTAGDBG_SET (0x000000b4) +#define HW_DIGCTL_SJTAGDBG_CLR (0x000000b8) +#define HW_DIGCTL_SJTAGDBG_TOG (0x000000bc) + +#define BP_DIGCTL_SJTAGDBG_RSVD2 27 +#define BM_DIGCTL_SJTAGDBG_RSVD2 0xF8000000 +#define BF_DIGCTL_SJTAGDBG_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_SJTAGDBG_RSVD2) +#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 +#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x07FF0000 +#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) \ + (((v) << 16) & BM_DIGCTL_SJTAGDBG_SJTAG_STATE) +#define BP_DIGCTL_SJTAGDBG_RSVD1 11 +#define BM_DIGCTL_SJTAGDBG_RSVD1 0x0000F800 +#define BF_DIGCTL_SJTAGDBG_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_SJTAGDBG_RSVD1) +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x00000400 +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x00000200 +#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x00000100 +#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 +#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0x000000F0 +#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) \ + (((v) << 4) & BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE) +#define BM_DIGCTL_SJTAGDBG_ACTIVE 0x00000008 +#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x00000004 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x00000002 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x00000001 + +#define HW_DIGCTL_MICROSECONDS (0x000000c0) +#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4) +#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8) +#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc) + +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v) + +#define HW_DIGCTL_DBGRD (0x000000d0) + +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v) + +#define HW_DIGCTL_DBG (0x000000e0) + +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF +#define BF_DIGCTL_DBG_VALUE(v) (v) + +#define HW_DIGCTL_OCRAM_BIST_CSR (0x000000f0) +#define HW_DIGCTL_OCRAM_BIST_CSR_SET (0x000000f4) +#define HW_DIGCTL_OCRAM_BIST_CSR_CLR (0x000000f8) +#define HW_DIGCTL_OCRAM_BIST_CSR_TOG (0x000000fc) + +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xFFFFF800 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD1) +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x00000400 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x00000200 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x00000100 +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD0) +#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x00000008 +#define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x00000004 +#define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x00000002 +#define BM_DIGCTL_OCRAM_BIST_CSR_START 0x00000001 + +#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110) +#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114) +#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118) +#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c) + +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120) +#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124) +#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128) +#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c) + +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130) +#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134) +#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138) +#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c) + +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140) +#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144) +#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148) +#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c) + +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150) +#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154) +#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158) +#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c) + +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160) +#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164) +#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168) +#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c) + +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170) +#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174) +#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178) +#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c) + +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180) +#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184) +#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188) +#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c) + +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190) +#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194) +#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198) +#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c) + +#define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS8_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01) +#define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS8_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00) + +#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0) +#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4) +#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8) +#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac) + +#define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS9_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11) +#define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS9_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10) + +#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0) +#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4) +#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8) +#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc) + +#define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS10_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21) +#define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS10_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20) + +#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0) +#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4) +#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8) +#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc) + +#define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS11_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31) +#define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS11_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30) + +#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0) +#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4) +#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8) +#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc) + +#define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS12_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS12_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS12_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS12_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00) + +#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0) +#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4) +#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8) +#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec) + +#define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS13_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS13_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS13_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS13_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20) + +#define HW_DIGCTL_SCRATCH0 (0x00000290) + +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH0_PTR(v) (v) + +#define HW_DIGCTL_SCRATCH1 (0x000002a0) + +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH1_PTR(v) (v) + +#define HW_DIGCTL_ARMCACHE (0x000002b0) + +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) \ + (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4) +#define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \ + (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS) +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) \ + (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3) +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \ + (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS) +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) \ + (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \ + (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS) +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) \ + (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \ + (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS) +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C +#define BF_DIGCTL_ARMCACHE_RSVD0(v) \ + (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \ + (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x000002c0) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x000002d0) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_SGTL (0x00000300) + +#define BP_DIGCTL_SGTL_COPYRIGHT 0 +#define BM_DIGCTL_SGTL_COPYRIGHT 0xFFFFFFFF +#define BF_DIGCTL_SGTL_COPYRIGHT(v) (v) + +#define HW_DIGCTL_CHIPID (0x00000310) + +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \ + (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE) +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00 +#define BF_DIGCTL_CHIPID_RSVD0(v) \ + (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0x000000FF +#define BF_DIGCTL_CHIPID_REVISION(v) \ + (((v) << 0) & BM_DIGCTL_CHIPID_REVISION) + +#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330) + +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xF0000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_AHB_STATS_SELECT_RSVD3) +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x0F000000 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \ + (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0x00F00000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_AHB_STATS_SELECT_RSVD2) +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x000F0000 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \ + (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0x0000F000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_AHB_STATS_SELECT_RSVD1) +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x00000F00 +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0x000000F0 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0) +#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0x0000000F +#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) \ + (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 + +#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x00000340) + +#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_STALLED (0x00000350) + +#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_CYCLES (0x00000360) + +#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370) + +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380) + +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390) + +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0) + +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0) + +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0) + +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0) + +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0) + +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0) + +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v) + +/* + * multi-register-define name HW_DIGCTL_MPTEn_LOC + * base 0x00000400 + * count 16 + * offset 0x10 + */ +#define HW_DIGCTL_MPTEn_LOC(n) (0x00000400 + (n) * 0x10) +#define BP_DIGCTL_MPTEn_LOC_RSVD0 12 +#define BM_DIGCTL_MPTEn_LOC_RSVD0 0xFFFFF000 +#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTEn_LOC_RSVD0) +#define BP_DIGCTL_MPTEn_LOC_LOC 0 +#define BM_DIGCTL_MPTEn_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTEn_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTEn_LOC_LOC) + +#define HW_DIGCTL_EMICLK_DELAY (0x00000500) + +#define BP_DIGCTL_EMICLK_DELAY_RSVD0 5 +#define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xFFFFFFE0 +#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_EMICLK_DELAY_RSVD0) +#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 +#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x0000001F +#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) \ + (((v) << 0) & BM_DIGCTL_EMICLK_DELAY_NUM_TAPS) +#endif /* __ARCH_ARM___DIGCTL_H */ diff --git a/arch/arm/mach-mx23/regs-pinctrl.h b/arch/arm/mach-mx23/regs-pinctrl.h new file mode 100644 index 000000000000..d38f7bdca051 --- /dev/null +++ b/arch/arm/mach-mx23/regs-pinctrl.h @@ -0,0 +1,1879 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 28 +#define BM_PINCTRL_CTRL_RSRVD2 0x30000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 +#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 +#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 +#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 +#define BP_PINCTRL_CTRL_RSRVD1 3 +#define BM_PINCTRL_CTRL_RSRVD1 0x00FFFFF8 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 3) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) + +#define BP_PINCTRL_MUXSEL0_BANK0_PIN15 30 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL0_BANK0_PIN15) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN14 28 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL0_BANK0_PIN14) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN13 26 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL0_BANK0_PIN13) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN12 24 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL0_BANK0_PIN12) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN11 22 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL0_BANK0_PIN11) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN10 20 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL0_BANK0_PIN10) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN09 18 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL0_BANK0_PIN09) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN08 16 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_BANK0_PIN08) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) + +#define BP_PINCTRL_MUXSEL1_BANK0_PIN31 30 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL1_BANK0_PIN31) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN30 28 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL1_BANK0_PIN30) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN29 26 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_BANK0_PIN29) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) + +#define BP_PINCTRL_MUXSEL3_RSRVD0 30 +#define BM_PINCTRL_MUXSEL3_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL3_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_RSRVD0) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN11 22 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_BANK2_PIN11) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) + +#define BP_PINCTRL_MUXSEL5_BANK2_PIN31 30 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL5_BANK2_PIN31) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN30 28 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL5_BANK2_PIN30) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN29 26 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL5_BANK2_PIN29) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN28 24 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_BANK2_PIN28) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN23 14 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL5_BANK2_PIN23) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN22 12 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_BANK2_PIN22) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) + +#define BP_PINCTRL_MUXSEL7_RSRVD0 12 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0xFFFFF000 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN19 6 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_BANK3_PIN19) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000200) +#define HW_PINCTRL_DRIVE0_SET (0x00000204) +#define HW_PINCTRL_DRIVE0_CLR (0x00000208) +#define HW_PINCTRL_DRIVE0_TOG (0x0000020c) + +#define BP_PINCTRL_DRIVE0_RSRVD7 30 +#define BM_PINCTRL_DRIVE0_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE0_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE0_RSRVD7) +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BP_PINCTRL_DRIVE0_RSRVD6 26 +#define BM_PINCTRL_DRIVE0_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE0_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE0_RSRVD6) +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BP_PINCTRL_DRIVE0_RSRVD5 22 +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE0_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE0_RSRVD5) +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BP_PINCTRL_DRIVE0_RSRVD4 18 +#define BM_PINCTRL_DRIVE0_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE0_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE0_RSRVD4) +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BP_PINCTRL_DRIVE0_RSRVD3 14 +#define BM_PINCTRL_DRIVE0_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE0_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE0_RSRVD3) +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BP_PINCTRL_DRIVE0_RSRVD2 10 +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE0_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE0_RSRVD2) +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BP_PINCTRL_DRIVE0_RSRVD1 6 +#define BM_PINCTRL_DRIVE0_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE0_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE0_RSRVD1) +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BP_PINCTRL_DRIVE0_RSRVD0 2 +#define BM_PINCTRL_DRIVE0_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE0_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE0_RSRVD0) +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000210) +#define HW_PINCTRL_DRIVE1_SET (0x00000214) +#define HW_PINCTRL_DRIVE1_CLR (0x00000218) +#define HW_PINCTRL_DRIVE1_TOG (0x0000021c) + +#define BP_PINCTRL_DRIVE1_RSRVD7 30 +#define BM_PINCTRL_DRIVE1_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE1_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE1_RSRVD7) +#define BP_PINCTRL_DRIVE1_BANK0_PIN15_MA 28 +#define BM_PINCTRL_DRIVE1_BANK0_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE1_BANK0_PIN15_MA) +#define BP_PINCTRL_DRIVE1_RSRVD6 26 +#define BM_PINCTRL_DRIVE1_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE1_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE1_RSRVD6) +#define BP_PINCTRL_DRIVE1_BANK0_PIN14_MA 24 +#define BM_PINCTRL_DRIVE1_BANK0_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE1_BANK0_PIN14_MA) +#define BP_PINCTRL_DRIVE1_RSRVD5 22 +#define BM_PINCTRL_DRIVE1_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE1_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE1_RSRVD5) +#define BP_PINCTRL_DRIVE1_BANK0_PIN13_MA 20 +#define BM_PINCTRL_DRIVE1_BANK0_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE1_BANK0_PIN13_MA) +#define BP_PINCTRL_DRIVE1_RSRVD4 18 +#define BM_PINCTRL_DRIVE1_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE1_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE1_RSRVD4) +#define BP_PINCTRL_DRIVE1_BANK0_PIN12_MA 16 +#define BM_PINCTRL_DRIVE1_BANK0_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE1_BANK0_PIN12_MA) +#define BP_PINCTRL_DRIVE1_RSRVD3 14 +#define BM_PINCTRL_DRIVE1_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE1_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE1_RSRVD3) +#define BP_PINCTRL_DRIVE1_BANK0_PIN11_MA 12 +#define BM_PINCTRL_DRIVE1_BANK0_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE1_BANK0_PIN11_MA) +#define BP_PINCTRL_DRIVE1_RSRVD2 10 +#define BM_PINCTRL_DRIVE1_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE1_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE1_RSRVD2) +#define BP_PINCTRL_DRIVE1_BANK0_PIN10_MA 8 +#define BM_PINCTRL_DRIVE1_BANK0_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE1_BANK0_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE1_BANK0_PIN10_MA) +#define BP_PINCTRL_DRIVE1_RSRVD1 6 +#define BM_PINCTRL_DRIVE1_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE1_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE1_RSRVD1) +#define BP_PINCTRL_DRIVE1_BANK0_PIN09_MA 4 +#define BM_PINCTRL_DRIVE1_BANK0_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE1_BANK0_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE1_BANK0_PIN09_MA) +#define BP_PINCTRL_DRIVE1_RSRVD0 2 +#define BM_PINCTRL_DRIVE1_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE1_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE1_RSRVD0) +#define BP_PINCTRL_DRIVE1_BANK0_PIN08_MA 0 +#define BM_PINCTRL_DRIVE1_BANK0_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE1_BANK0_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE1_BANK0_PIN08_MA) + +#define HW_PINCTRL_DRIVE2 (0x00000220) +#define HW_PINCTRL_DRIVE2_SET (0x00000224) +#define HW_PINCTRL_DRIVE2_CLR (0x00000228) +#define HW_PINCTRL_DRIVE2_TOG (0x0000022c) + +#define BP_PINCTRL_DRIVE2_RSRVD7 30 +#define BM_PINCTRL_DRIVE2_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE2_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE2_RSRVD7) +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BP_PINCTRL_DRIVE2_RSRVD6 26 +#define BM_PINCTRL_DRIVE2_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE2_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE2_RSRVD6) +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BP_PINCTRL_DRIVE2_RSRVD5 22 +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE2_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE2_RSRVD5) +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BP_PINCTRL_DRIVE2_RSRVD4 18 +#define BM_PINCTRL_DRIVE2_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE2_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE2_RSRVD4) +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BP_PINCTRL_DRIVE2_RSRVD3 14 +#define BM_PINCTRL_DRIVE2_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE2_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE2_RSRVD3) +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BP_PINCTRL_DRIVE2_RSRVD2 10 +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE2_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE2_RSRVD2) +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BP_PINCTRL_DRIVE2_RSRVD1 6 +#define BM_PINCTRL_DRIVE2_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE2_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE2_RSRVD1) +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BP_PINCTRL_DRIVE2_RSRVD0 2 +#define BM_PINCTRL_DRIVE2_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE2_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE2_RSRVD0) +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000230) +#define HW_PINCTRL_DRIVE3_SET (0x00000234) +#define HW_PINCTRL_DRIVE3_CLR (0x00000238) +#define HW_PINCTRL_DRIVE3_TOG (0x0000023c) + +#define BP_PINCTRL_DRIVE3_RSRVD7 30 +#define BM_PINCTRL_DRIVE3_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE3_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE3_RSRVD7) +#define BP_PINCTRL_DRIVE3_BANK0_PIN31_MA 28 +#define BM_PINCTRL_DRIVE3_BANK0_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE3_BANK0_PIN31_MA) +#define BP_PINCTRL_DRIVE3_RSRVD6 26 +#define BM_PINCTRL_DRIVE3_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE3_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE3_RSRVD6) +#define BP_PINCTRL_DRIVE3_BANK0_PIN30_MA 24 +#define BM_PINCTRL_DRIVE3_BANK0_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE3_BANK0_PIN30_MA) +#define BP_PINCTRL_DRIVE3_RSRVD5 22 +#define BM_PINCTRL_DRIVE3_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BP_PINCTRL_DRIVE3_BANK0_PIN29_MA 20 +#define BM_PINCTRL_DRIVE3_BANK0_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_BANK0_PIN29_MA) +#define BP_PINCTRL_DRIVE3_RSRVD4 18 +#define BM_PINCTRL_DRIVE3_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE3_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE3_RSRVD4) +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BP_PINCTRL_DRIVE3_RSRVD3 14 +#define BM_PINCTRL_DRIVE3_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE3_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE3_RSRVD3) +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BP_PINCTRL_DRIVE3_RSRVD2 10 +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE3_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE3_RSRVD2) +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BP_PINCTRL_DRIVE3_RSRVD1 6 +#define BM_PINCTRL_DRIVE3_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE3_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE3_RSRVD1) +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BP_PINCTRL_DRIVE3_RSRVD0 2 +#define BM_PINCTRL_DRIVE3_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE3_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE3_RSRVD0) +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000240) +#define HW_PINCTRL_DRIVE4_SET (0x00000244) +#define HW_PINCTRL_DRIVE4_CLR (0x00000248) +#define HW_PINCTRL_DRIVE4_TOG (0x0000024c) + +#define BP_PINCTRL_DRIVE4_RSRVD7 30 +#define BM_PINCTRL_DRIVE4_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE4_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE4_RSRVD7) +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BP_PINCTRL_DRIVE4_RSRVD6 26 +#define BM_PINCTRL_DRIVE4_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE4_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE4_RSRVD6) +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BP_PINCTRL_DRIVE4_RSRVD5 22 +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE4_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE4_RSRVD5) +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BP_PINCTRL_DRIVE4_RSRVD4 18 +#define BM_PINCTRL_DRIVE4_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE4_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE4_RSRVD4) +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BP_PINCTRL_DRIVE4_RSRVD3 14 +#define BM_PINCTRL_DRIVE4_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE4_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE4_RSRVD3) +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BP_PINCTRL_DRIVE4_RSRVD2 10 +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE4_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE4_RSRVD2) +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BP_PINCTRL_DRIVE4_RSRVD1 6 +#define BM_PINCTRL_DRIVE4_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE4_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE4_RSRVD1) +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BP_PINCTRL_DRIVE4_RSRVD0 2 +#define BM_PINCTRL_DRIVE4_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE4_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE4_RSRVD0) +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000250) +#define HW_PINCTRL_DRIVE5_SET (0x00000254) +#define HW_PINCTRL_DRIVE5_CLR (0x00000258) +#define HW_PINCTRL_DRIVE5_TOG (0x0000025c) + +#define BP_PINCTRL_DRIVE5_RSRVD7 30 +#define BM_PINCTRL_DRIVE5_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE5_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE5_RSRVD7) +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BP_PINCTRL_DRIVE5_RSRVD6 26 +#define BM_PINCTRL_DRIVE5_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE5_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE5_RSRVD6) +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BP_PINCTRL_DRIVE5_RSRVD5 22 +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE5_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE5_RSRVD5) +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BP_PINCTRL_DRIVE5_RSRVD4 18 +#define BM_PINCTRL_DRIVE5_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE5_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE5_RSRVD4) +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BP_PINCTRL_DRIVE5_RSRVD3 14 +#define BM_PINCTRL_DRIVE5_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE5_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE5_RSRVD3) +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BP_PINCTRL_DRIVE5_RSRVD2 10 +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE5_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE5_RSRVD2) +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BP_PINCTRL_DRIVE5_RSRVD1 6 +#define BM_PINCTRL_DRIVE5_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE5_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE5_RSRVD1) +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BP_PINCTRL_DRIVE5_RSRVD0 2 +#define BM_PINCTRL_DRIVE5_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE5_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE5_RSRVD0) +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000260) +#define HW_PINCTRL_DRIVE6_SET (0x00000264) +#define HW_PINCTRL_DRIVE6_CLR (0x00000268) +#define HW_PINCTRL_DRIVE6_TOG (0x0000026c) + +#define BP_PINCTRL_DRIVE6_RSRVD7 30 +#define BM_PINCTRL_DRIVE6_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE6_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE6_RSRVD7) +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BP_PINCTRL_DRIVE6_RSRVD6 26 +#define BM_PINCTRL_DRIVE6_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE6_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE6_RSRVD6) +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BP_PINCTRL_DRIVE6_RSRVD5 22 +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE6_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE6_RSRVD5) +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BP_PINCTRL_DRIVE6_RSRVD4 18 +#define BM_PINCTRL_DRIVE6_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE6_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE6_RSRVD4) +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BP_PINCTRL_DRIVE6_RSRVD3 14 +#define BM_PINCTRL_DRIVE6_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE6_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE6_RSRVD3) +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BP_PINCTRL_DRIVE6_RSRVD2 10 +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE6_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE6_RSRVD2) +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BP_PINCTRL_DRIVE6_RSRVD1 6 +#define BM_PINCTRL_DRIVE6_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE6_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE6_RSRVD1) +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BP_PINCTRL_DRIVE6_RSRVD0 2 +#define BM_PINCTRL_DRIVE6_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE6_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE6_RSRVD0) +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000270) +#define HW_PINCTRL_DRIVE7_SET (0x00000274) +#define HW_PINCTRL_DRIVE7_CLR (0x00000278) +#define HW_PINCTRL_DRIVE7_TOG (0x0000027c) + +#define BP_PINCTRL_DRIVE7_RSRVD7 28 +#define BM_PINCTRL_DRIVE7_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE7_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_RSRVD7) +#define BP_PINCTRL_DRIVE7_RSRVD6 26 +#define BM_PINCTRL_DRIVE7_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE7_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE7_RSRVD6) +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BP_PINCTRL_DRIVE7_RSRVD5 22 +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE7_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE7_RSRVD5) +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BP_PINCTRL_DRIVE7_RSRVD4 18 +#define BM_PINCTRL_DRIVE7_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE7_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE7_RSRVD4) +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BP_PINCTRL_DRIVE7_RSRVD3 14 +#define BM_PINCTRL_DRIVE7_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE7_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE7_RSRVD3) +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BP_PINCTRL_DRIVE7_RSRVD2 10 +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE7_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE7_RSRVD2) +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BP_PINCTRL_DRIVE7_RSRVD1 6 +#define BM_PINCTRL_DRIVE7_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE7_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE7_RSRVD1) +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BP_PINCTRL_DRIVE7_RSRVD0 2 +#define BM_PINCTRL_DRIVE7_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE7_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE7_RSRVD0) +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000280) +#define HW_PINCTRL_DRIVE8_SET (0x00000284) +#define HW_PINCTRL_DRIVE8_CLR (0x00000288) +#define HW_PINCTRL_DRIVE8_TOG (0x0000028c) + +#define BP_PINCTRL_DRIVE8_RSRVD7 30 +#define BM_PINCTRL_DRIVE8_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE8_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE8_RSRVD7) +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BP_PINCTRL_DRIVE8_RSRVD6 26 +#define BM_PINCTRL_DRIVE8_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE8_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE8_RSRVD6) +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BP_PINCTRL_DRIVE8_RSRVD5 22 +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE8_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE8_RSRVD5) +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BP_PINCTRL_DRIVE8_RSRVD4 18 +#define BM_PINCTRL_DRIVE8_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE8_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE8_RSRVD4) +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BP_PINCTRL_DRIVE8_RSRVD3 14 +#define BM_PINCTRL_DRIVE8_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE8_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE8_RSRVD3) +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BP_PINCTRL_DRIVE8_RSRVD2 10 +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE8_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE8_RSRVD2) +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BP_PINCTRL_DRIVE8_RSRVD1 6 +#define BM_PINCTRL_DRIVE8_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE8_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE8_RSRVD1) +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BP_PINCTRL_DRIVE8_RSRVD0 2 +#define BM_PINCTRL_DRIVE8_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE8_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE8_RSRVD0) +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000290) +#define HW_PINCTRL_DRIVE9_SET (0x00000294) +#define HW_PINCTRL_DRIVE9_CLR (0x00000298) +#define HW_PINCTRL_DRIVE9_TOG (0x0000029c) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BM_PINCTRL_DRIVE9_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN11_MA 12 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_BANK2_PIN11_MA) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BP_PINCTRL_DRIVE9_RSRVD0 2 +#define BM_PINCTRL_DRIVE9_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE9_RSRVD0) +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000002a0) +#define HW_PINCTRL_DRIVE10_SET (0x000002a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000002a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000002ac) + +#define BM_PINCTRL_DRIVE10_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN23_MA 28 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE10_BANK2_PIN23_MA) +#define BM_PINCTRL_DRIVE10_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN22_MA 24 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_BANK2_PIN22_MA) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000002b0) +#define HW_PINCTRL_DRIVE11_SET (0x000002b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000002b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000002bc) + +#define BM_PINCTRL_DRIVE11_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN31_MA 28 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE11_BANK2_PIN31_MA) +#define BM_PINCTRL_DRIVE11_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN30_MA 24 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE11_BANK2_PIN30_MA) +#define BM_PINCTRL_DRIVE11_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN29_MA 20 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE11_BANK2_PIN29_MA) +#define BP_PINCTRL_DRIVE11_RSRVD4 18 +#define BM_PINCTRL_DRIVE11_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BP_PINCTRL_DRIVE11_BANK2_PIN28_MA 16 +#define BM_PINCTRL_DRIVE11_BANK2_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_BANK2_PIN28_MA) +#define BP_PINCTRL_DRIVE11_RSRVD3 14 +#define BM_PINCTRL_DRIVE11_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE11_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE11_RSRVD3) +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000002c0) +#define HW_PINCTRL_DRIVE12_SET (0x000002c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000002c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000002cc) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000002d0) +#define HW_PINCTRL_DRIVE13_SET (0x000002d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000002d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000002dc) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000002e0) +#define HW_PINCTRL_DRIVE14_SET (0x000002e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000002e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000002ec) + +#define BP_PINCTRL_DRIVE14_RSRVD6 24 +#define BM_PINCTRL_DRIVE14_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE14_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_RSRVD6) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BM_PINCTRL_DRIVE14_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN19_MA 12 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_BANK3_PIN19_MA) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_PULL0 (0x00000400) +#define HW_PINCTRL_PULL0_SET (0x00000404) +#define HW_PINCTRL_PULL0_CLR (0x00000408) +#define HW_PINCTRL_PULL0_TOG (0x0000040c) + +#define BM_PINCTRL_PULL0_BANK0_PIN31 0x80000000 +#define BM_PINCTRL_PULL0_BANK0_PIN30 0x40000000 +#define BM_PINCTRL_PULL0_BANK0_PIN29 0x20000000 +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BP_PINCTRL_PULL0_RSRVD2 23 +#define BM_PINCTRL_PULL0_RSRVD2 0x03800000 +#define BF_PINCTRL_PULL0_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL0_RSRVD2) +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BP_PINCTRL_PULL0_RSRVD1 16 +#define BM_PINCTRL_PULL0_RSRVD1 0x00030000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 16) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN15 0x00008000 +#define BP_PINCTRL_PULL0_RSRVD0 12 +#define BM_PINCTRL_PULL0_RSRVD0 0x00007000 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN11 0x00000800 +#define BM_PINCTRL_PULL0_BANK0_PIN10 0x00000400 +#define BM_PINCTRL_PULL0_BANK0_PIN09 0x00000200 +#define BM_PINCTRL_PULL0_BANK0_PIN08 0x00000100 +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000410) +#define HW_PINCTRL_PULL1_SET (0x00000414) +#define HW_PINCTRL_PULL1_CLR (0x00000418) +#define HW_PINCTRL_PULL1_TOG (0x0000041c) + +#define BP_PINCTRL_PULL1_RSRVD3 29 +#define BM_PINCTRL_PULL1_RSRVD3 0xE0000000 +#define BF_PINCTRL_PULL1_RSRVD3(v) \ + (((v) << 29) & BM_PINCTRL_PULL1_RSRVD3) +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BP_PINCTRL_PULL1_RSRVD2 23 +#define BM_PINCTRL_PULL1_RSRVD2 0x0F800000 +#define BF_PINCTRL_PULL1_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL1_RSRVD2) +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BP_PINCTRL_PULL1_RSRVD1 19 +#define BM_PINCTRL_PULL1_RSRVD1 0x00380000 +#define BF_PINCTRL_PULL1_RSRVD1(v) \ + (((v) << 19) & BM_PINCTRL_PULL1_RSRVD1) +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BP_PINCTRL_PULL1_RSRVD0 0 +#define BM_PINCTRL_PULL1_RSRVD0 0x0003FFFF +#define BF_PINCTRL_PULL1_RSRVD0(v) \ + (((v) << 0) & BM_PINCTRL_PULL1_RSRVD0) + +#define HW_PINCTRL_PULL2 (0x00000420) +#define HW_PINCTRL_PULL2_SET (0x00000424) +#define HW_PINCTRL_PULL2_CLR (0x00000428) +#define HW_PINCTRL_PULL2_TOG (0x0000042c) + +#define BP_PINCTRL_PULL2_RSRVD2 29 +#define BM_PINCTRL_PULL2_RSRVD2 0xE0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 29) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN28 0x10000000 +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BP_PINCTRL_PULL2_RSRVD1 9 +#define BM_PINCTRL_PULL2_RSRVD1 0x07FFFE00 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 9) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BP_PINCTRL_PULL2_RSRVD0 6 +#define BM_PINCTRL_PULL2_RSRVD0 0x000000C0 +#define BF_PINCTRL_PULL2_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_PULL2_RSRVD0) +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000430) +#define HW_PINCTRL_PULL3_SET (0x00000434) +#define HW_PINCTRL_PULL3_CLR (0x00000438) +#define HW_PINCTRL_PULL3_TOG (0x0000043c) + +#define BP_PINCTRL_PULL3_RSRVD0 18 +#define BM_PINCTRL_PULL3_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_PULL3_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_PULL3_RSRVD0) +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000500) +#define HW_PINCTRL_DOUT0_SET (0x00000504) +#define HW_PINCTRL_DOUT0_CLR (0x00000508) +#define HW_PINCTRL_DOUT0_TOG (0x0000050c) + +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) (v) + +#define HW_PINCTRL_DOUT1 (0x00000510) +#define HW_PINCTRL_DOUT1_SET (0x00000514) +#define HW_PINCTRL_DOUT1_CLR (0x00000518) +#define HW_PINCTRL_DOUT1_TOG (0x0000051c) + +#define BM_PINCTRL_DOUT1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT1_DOUT) + +#define HW_PINCTRL_DOUT2 (0x00000520) +#define HW_PINCTRL_DOUT2_SET (0x00000524) +#define HW_PINCTRL_DOUT2_CLR (0x00000528) +#define HW_PINCTRL_DOUT2_TOG (0x0000052c) + +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) (v) + +#define HW_PINCTRL_DIN0 (0x00000600) +#define HW_PINCTRL_DIN0_SET (0x00000604) +#define HW_PINCTRL_DIN0_CLR (0x00000608) +#define HW_PINCTRL_DIN0_TOG (0x0000060c) + +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) (v) + +#define HW_PINCTRL_DIN1 (0x00000610) +#define HW_PINCTRL_DIN1_SET (0x00000614) +#define HW_PINCTRL_DIN1_CLR (0x00000618) +#define HW_PINCTRL_DIN1_TOG (0x0000061c) + +#define BM_PINCTRL_DIN1_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN1_DIN) + +#define HW_PINCTRL_DIN2 (0x00000620) +#define HW_PINCTRL_DIN2_SET (0x00000624) +#define HW_PINCTRL_DIN2_CLR (0x00000628) +#define HW_PINCTRL_DIN2_TOG (0x0000062c) + +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) (v) + +#define HW_PINCTRL_DOE0 (0x00000700) +#define HW_PINCTRL_DOE0_SET (0x00000704) +#define HW_PINCTRL_DOE0_CLR (0x00000708) +#define HW_PINCTRL_DOE0_TOG (0x0000070c) + +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) (v) + +#define HW_PINCTRL_DOE1 (0x00000710) +#define HW_PINCTRL_DOE1_SET (0x00000714) +#define HW_PINCTRL_DOE1_CLR (0x00000718) +#define HW_PINCTRL_DOE1_TOG (0x0000071c) + +#define BM_PINCTRL_DOE1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE1_DOE) + +#define HW_PINCTRL_DOE2 (0x00000720) +#define HW_PINCTRL_DOE2_SET (0x00000724) +#define HW_PINCTRL_DOE2_CLR (0x00000728) +#define HW_PINCTRL_DOE2_TOG (0x0000072c) + +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) (v) + +#define HW_PINCTRL_PIN2IRQ0 (0x00000800) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00000804) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00000808) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000080c) + +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ1 (0x00000810) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00000814) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00000818) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000081c) + +#define BM_PINCTRL_PIN2IRQ1_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ1_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ2 (0x00000820) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00000824) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00000828) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000082c) + +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) (v) + +#define HW_PINCTRL_IRQEN0 (0x00000900) +#define HW_PINCTRL_IRQEN0_SET (0x00000904) +#define HW_PINCTRL_IRQEN0_CLR (0x00000908) +#define HW_PINCTRL_IRQEN0_TOG (0x0000090c) + +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN1 (0x00000910) +#define HW_PINCTRL_IRQEN1_SET (0x00000914) +#define HW_PINCTRL_IRQEN1_CLR (0x00000918) +#define HW_PINCTRL_IRQEN1_TOG (0x0000091c) + +#define BM_PINCTRL_IRQEN1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN1_IRQEN) + +#define HW_PINCTRL_IRQEN2 (0x00000920) +#define HW_PINCTRL_IRQEN2_SET (0x00000924) +#define HW_PINCTRL_IRQEN2_CLR (0x00000928) +#define HW_PINCTRL_IRQEN2_TOG (0x0000092c) + +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) (v) + +#define HW_PINCTRL_IRQLEVEL0 (0x00000a00) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00000a04) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00000a08) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x00000a0c) + +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL1 (0x00000a10) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00000a14) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00000a18) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x00000a1c) + +#define BM_PINCTRL_IRQLEVEL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL1_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL2 (0x00000a20) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00000a24) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00000a28) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x00000a2c) + +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQPOL0 (0x00000b00) +#define HW_PINCTRL_IRQPOL0_SET (0x00000b04) +#define HW_PINCTRL_IRQPOL0_CLR (0x00000b08) +#define HW_PINCTRL_IRQPOL0_TOG (0x00000b0c) + +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL1 (0x00000b10) +#define HW_PINCTRL_IRQPOL1_SET (0x00000b14) +#define HW_PINCTRL_IRQPOL1_CLR (0x00000b18) +#define HW_PINCTRL_IRQPOL1_TOG (0x00000b1c) + +#define BM_PINCTRL_IRQPOL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL1_IRQPOL) + +#define HW_PINCTRL_IRQPOL2 (0x00000b20) +#define HW_PINCTRL_IRQPOL2_SET (0x00000b24) +#define HW_PINCTRL_IRQPOL2_CLR (0x00000b28) +#define HW_PINCTRL_IRQPOL2_TOG (0x00000b2c) + +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQSTAT0 (0x00000c00) +#define HW_PINCTRL_IRQSTAT0_SET (0x00000c04) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00000c08) +#define HW_PINCTRL_IRQSTAT0_TOG (0x00000c0c) + +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT1 (0x00000c10) +#define HW_PINCTRL_IRQSTAT1_SET (0x00000c14) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00000c18) +#define HW_PINCTRL_IRQSTAT1_TOG (0x00000c1c) + +#define BM_PINCTRL_IRQSTAT1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT1_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT2 (0x00000c20) +#define HW_PINCTRL_IRQSTAT2_SET (0x00000c24) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00000c28) +#define HW_PINCTRL_IRQSTAT2_TOG (0x00000c2c) + +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) (v) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-mx23/serial.c b/arch/arm/mach-mx23/serial.c new file mode 100644 index 000000000000..5f60d4844d5a --- /dev/null +++ b/arch/arm/mach-mx23/serial.c @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is distributed in the hope that it will be useful, + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/dma.h> +#include "device.h" + +#if defined(CONFIG_SERIAL_MXS_AUART) || \ + defined(CONFIG_SERIAL_MXS_AUART_MODULE) + +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE +static struct resource auart0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART0_PHYS_ADDR, + .end = AUART0_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0, + .end = IRQ_AUART0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_RX_DMA, + .end = IRQ_AUART0_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_TX_DMA, + .end = IRQ_AUART0_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart0_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART0_DMA_ENABLE + .dma_mode = 1, +#endif + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE +static struct resource auart1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART1_PHYS_ADDR, + .end = AUART1_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1, + .end = IRQ_AUART1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_RX_DMA, + .end = IRQ_AUART1_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_TX_DMA, + .end = IRQ_AUART1_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart1_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART1_DMA_ENABLE + .dma_mode = 1, +#endif + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE +static struct resource auart2_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART2_PHYS_ADDR, + .end = AUART2_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2, + .end = IRQ_AUART2, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_RX_DMA, + .end = IRQ_AUART2_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_TX_DMA, + .end = IRQ_AUART2_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart2_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART2_DMA_ENABLE + .dma_mode = 1, +#endif + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE +static struct resource auart3_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART3_PHYS_ADDR, + .end = AUART3_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3, + .end = IRQ_AUART3, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_RX_DMA, + .end = IRQ_AUART3_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_TX_DMA, + .end = IRQ_AUART3_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart3_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART3_DMA_ENABLE + .dma_mode = 1, +#endif + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE +static struct resource auart4_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART4_PHYS_ADDR, + .end = AUART4_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4, + .end = IRQ_AUART4, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_RX_DMA, + .end = IRQ_AUART4_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_TX_DMA, + .end = IRQ_AUART4_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart4_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART4_DMA_ENABLE + .dma_mode = 1, +#endif + .timeout = HZ, +}; +#endif + +void __init mx28_init_auart(void) +{ + int i; + struct mxs_dev_lookup *plookup; + struct platform_device *pdev; + + plookup = mxs_get_devices("mxs-auart"); + if (plookup == NULL || IS_ERR(plookup)) + return; + for (i = 0; i < plookup->size; i++) { + pdev = plookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + case 0: + pdev->resource = auart0_resource; + pdev->num_resources = ARRAY_SIZE(auart0_resource); + pdev->dev.platform_data = &mxs_auart0_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + case 1: + pdev->resource = auart1_resource; + pdev->num_resources = ARRAY_SIZE(auart1_resource); + pdev->dev.platform_data = &mxs_auart1_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + case 2: + pdev->resource = auart2_resource; + pdev->num_resources = ARRAY_SIZE(auart2_resource); + pdev->dev.platform_data = &mxs_auart2_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + case 3: + pdev->resource = auart3_resource; + pdev->num_resources = ARRAY_SIZE(auart3_resource); + pdev->dev.platform_data = &mxs_auart3_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE + case 4: + pdev->resource = auart4_resource; + pdev->num_resources = ARRAY_SIZE(auart4_resource); + pdev->dev.platform_data = &mxs_auart4_platdata; + break; +#endif + default: + break; + } + mxs_add_device(pdev, 3); + } +} +#else +void __init mx28_init_auart(void) +{ +} +#endif diff --git a/arch/arm/mach-mx23/usb.h b/arch/arm/mach-mx23/usb.h new file mode 100644 index 000000000000..689603d4e7d6 --- /dev/null +++ b/arch/arm/mach-mx23/usb.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, + struct fsl_usb2_platform_data + *config); +extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable); +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff --git a/arch/arm/mach-mx23/usb_dr.c b/arch/arm/mach-mx23/usb_dr.c new file mode 100644 index 000000000000..69cb854366da --- /dev/null +++ b/arch/arm/mach-mx23/usb_dr.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <mach/irqs.h> +#include "usb.h" + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int usbotg_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usb_clk0"); + clk_enable(usb_clk); + clk_put(usb_clk); + + return usbotg_init(pdev); +} + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .phy_regs = USBPHY0_PHYS_ADDR, +}; + +/* + * resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{} + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + PDATA->change_ahb_burst = 1; + PDATA->ahb_burst_mode = 0; + return 0; +} + +module_init(usb_dr_init); diff --git a/arch/arm/mach-mx23/usb_h1.c b/arch/arm/mach-mx23/usb_h1.c new file mode 100644 index 000000000000..4ee6378c683f --- /dev/null +++ b/arch/arm/mach-mx23/usb_h1.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <mach/arc_otg.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/irqs.h> +#include "usb.h" + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int fsl_usb_host_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usb_clk1"); + clk_enable(usb_clk); + clk_put(usb_clk); + + return fsl_usb_host_init(pdev); +} + +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init_ext, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .phy_regs = USBPHY1_PHYS_ADDR, +}; + +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USBCTRL1_PHYS_ADDR), + .end = (u32) (USBCTRL1_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static int __init usbh1_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh1_resources, + ARRAY_SIZE(usbh1_resources), &usbh1_config); + + return 0; +} + +module_init(usbh1_init); diff --git a/arch/arm/plat-mxs/Kconfig b/arch/arm/plat-mxs/Kconfig index befd404a3f11..f67d9f3d26fb 100644 --- a/arch/arm/plat-mxs/Kconfig +++ b/arch/arm/plat-mxs/Kconfig @@ -15,12 +15,26 @@ config ARCH_MX28 ---help--- Support Freescale MX28 chips +config ARCH_MX23 + bool "Freescale MX23" + select CPU_ARM926T + select ZONE_DMA + select MXS_ICOLL + select MXS_DMA_ENGINE + select MXS_AUART_DMA_SUPPORT + ---help--- + Support Freescale MX23 chips + endchoice if ARCH_MX28 source arch/arm/mach-mx28/Kconfig endif +if ARCH_MX23 +source arch/arm/mach-mx23/Kconfig +endif + config DMA_ZONE_SIZE int "DMA memory zone size" range 0 32 diff --git a/arch/arm/plat-mxs/Makefile b/arch/arm/plat-mxs/Makefile index fb8c27b93c25..fa25e5e51a49 100644 --- a/arch/arm/plat-mxs/Makefile +++ b/arch/arm/plat-mxs/Makefile @@ -2,7 +2,9 @@ # Makefile for the linux kernel. # # Object file lists. -obj-y += core.o clock.o pinctrl.o device.o timer.o +obj-y += core.o clock.o pinctrl.o device.o timer-nomatch.o + +obj-$(CONFIG_MXS_TIMER_WITH_MACH) += timer-match.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/arm/plat-mxs/dma-apbh.c b/arch/arm/plat-mxs/dma-apbh.c index 221ff491cbea..9dfcadde02c9 100644 --- a/arch/arm/plat-mxs/dma-apbh.c +++ b/arch/arm/plat-mxs/dma-apbh.c @@ -28,6 +28,7 @@ #include <mach/device.h> #include <mach/dmaengine.h> +#include <mach/hardware.h> #include "regs-apbh.h" diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c index 40d299e9e812..6f412310648c 100644 --- a/arch/arm/plat-mxs/dma-apbx.c +++ b/arch/arm/plat-mxs/dma-apbx.c @@ -28,6 +28,7 @@ #include <mach/device.h> #include <mach/dmaengine.h> +#include <mach/hardware.h> #include "regs-apbx.h" diff --git a/arch/arm/plat-mxs/include/mach/debug-macro.S b/arch/arm/plat-mxs/include/mach/debug-macro.S new file mode 100644 index 000000000000..651bdcd378aa --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/debug-macro.S @@ -0,0 +1,42 @@ +/* + * Debugging macro include header + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <mach/hardware.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =MXS_LL_UART_PADDR @ physical + ldrne \rx, =MXS_LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0] @ data register at 0 + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h index 3aaed6d7c621..b424a69d256d 100644 --- a/arch/arm/plat-mxs/include/mach/device.h +++ b/arch/arm/plat-mxs/include/mach/device.h @@ -141,6 +141,7 @@ struct flexcan_platform_data { }; extern void mxs_timer_init(struct mxs_sys_timer *timer); +extern void mxs_nomatch_timer_init(struct mxs_sys_timer *timer); extern void mxs_nop_release(struct device *dev); extern int mxs_add_devices(struct platform_device *, int num, int level); diff --git a/arch/arm/plat-mxs/include/mach/hardware.h b/arch/arm/plat-mxs/include/mach/hardware.h index 7fdbd054bf41..c7dd8fe1d31b 100644 --- a/arch/arm/plat-mxs/include/mach/hardware.h +++ b/arch/arm/plat-mxs/include/mach/hardware.h @@ -26,6 +26,13 @@ # define cpu_is_mx28() 0 #endif +#ifdef CONFIG_ARCH_MX23 +# include <mach/mx23.h> +# define cpu_is_mx23() 1 +# else +# define cpu_is_mx23() 0 +#endif + #ifndef MXS_EXTEND_IRQS #define MXS_EXTEND_IRQS 0 #endif diff --git a/arch/arm/plat-mxs/timer.c b/arch/arm/plat-mxs/timer-match.c index 7d8f2477f4ba..7d8f2477f4ba 100644 --- a/arch/arm/plat-mxs/timer.c +++ b/arch/arm/plat-mxs/timer-match.c diff --git a/arch/arm/plat-mxs/timer-nomatch.c b/arch/arm/plat-mxs/timer-nomatch.c new file mode 100644 index 000000000000..91c9b2044357 --- /dev/null +++ b/arch/arm/plat-mxs/timer-nomatch.c @@ -0,0 +1,191 @@ +/* + * System timer for Freescale STMP37XX/STMP378X + * + * Embedded Alley Solutions, Inc <source@embeddedalley.com> + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/interrupt.h> + +#include <asm/mach/time.h> +#include <mach/hardware.h> +#include <mach/device.h> +#include <mach/regs-timrot.h> + +static struct mxs_sys_timer *online_timer; + +static irqreturn_t +mxs_nomatch_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* timer 0 */ + if (__raw_readl(online_timer->base + HW_TIMROT_TIMCTRLn(0)) & + BM_TIMROT_TIMCTRLn_IRQ) { + + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(0)); + c->event_handler(c); + } + + /* timer 1 */ + else if (__raw_readl(online_timer->base + HW_TIMROT_TIMCTRLn(1)) + & BM_TIMROT_TIMCTRLn_IRQ) { + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(1)); + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(1)); + __raw_writel(0xFFFF, + online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + } + + return IRQ_HANDLED; +} + +static cycle_t mxs_nomatch_clock_read(struct clocksource *cs) +{ + return ~((__raw_readl(online_timer->base + HW_TIMROT_TIMCOUNTn(1)) + & 0xFFFF0000) >> 16); +} + +static int +mxs_nomatch_timrot_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + /* reload the timer */ + __raw_writel(delta, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + return 0; +} + +static void +mxs_nomatch_timrot_set_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ +} + +static struct clock_event_device ckevt_timrot = { + .name = "timrot", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = mxs_nomatch_timrot_set_next_event, + .set_mode = mxs_nomatch_timrot_set_mode, +}; + +static struct clocksource cksrc_mxs_nomatch = { + .name = "mxs clock source", + .rating = 250, + .read = mxs_nomatch_clock_read, + .mask = CLOCKSOURCE_MASK(16), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static struct irqaction mxs_nomatch_timer_irq = { + .name = "mxs_nomatch_timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxs_nomatch_timer_interrupt, + .dev_id = &ckevt_timrot, +}; + + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +void mxs_nomatch_timer_init(struct mxs_sys_timer *timer) +{ + + if (online_timer) + return; + + online_timer = timer; + + cksrc_mxs_nomatch.mult = clocksource_hz2mult(CLOCK_TICK_RATE, + cksrc_mxs_nomatch.shift); + ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + ckevt_timrot.shift); + ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); + ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); + ckevt_timrot.cpumask = cpumask_of(0); + + /* clear two timers */ + __raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + + /* configure them */ + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(0)); + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(1)); + + __raw_writel(CLOCK_TICK_RATE / HZ - 1, + online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + + setup_irq(IRQ_TIMER0, &mxs_nomatch_timer_irq); + + clocksource_register(&cksrc_mxs_nomatch); + clockevents_register_device(&ckevt_timrot); +} + +#ifdef CONFIG_PM + +void mxs_nomatch_suspend_timer(void) +{ + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(0)); + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + online_timer->base + HW_TIMROT_ROTCTRL_SET); +} + +void mxs_nomatch_resume_timer(void) +{ + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, + online_timer->base + HW_TIMROT_ROTCTRL_CLR); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(0)); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(1)); + __raw_writel(CLOCK_TICK_RATE / HZ - 1, + online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); +} + +#else + +#define mxs_nomatch_suspend_timer NULL +#define mxs_nomatch_resume_timer NULL + +#endif /* CONFIG_PM */ diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index fc1549fd585f..641d3521fd52 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -2516,6 +2516,7 @@ swarco_itc3 MACH_SWARCO_ITC3 SWARCO_ITC3 2528 tx51 MACH_TX51 TX51 2529 dolby_cat1021 MACH_DOLBY_CAT1021 DOLBY_CAT1021 2530 mx28evk MACH_MX28EVK MX28EVK 2531 +mx23evk MACH_MX23EVK MX23EVK 2629 phoenix260 MACH_PHOENIX260 PHOENIX260 2532 uvaca_stork MACH_UVACA_STORK UVACA_STORK 2533 smartq5 MACH_SMARTQ5 SMARTQ5 2534 |